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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Added interrupt support (not exiting correctly yet), macros for causing traps.
This commit is contained in:
Kip Macsai-Goren
parent
b7a680ec2a
commit
88897da30b
@ -55,12 +55,17 @@ RVTEST_CODE_BEGIN
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.endm
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.macro TRAP_HANDLER MODE, VECTORED=1 // default to vectored tests
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// Set up the exception Handler, keeping the original handler in x4.
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.macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0
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// MODE decides which mode this trap handler will be taken in (M or S mode)
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// Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1)
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// vs Using the non-vector approach the rest of the trap handler takes (0)
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// DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1)
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// vs not saving that info to the signature (0)
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// trap handler setup
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// Set up the exception Handler, keeping the original handler in x4.
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la x1, trap_handler_\MODE\()
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.if (\VECTORED == 1)
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.if (\VECTORED\() == 1)
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ori x1, x1, 0x1 // set mode field of tvec to 1, forcing vectored interrupts
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.endif
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@ -115,17 +120,18 @@ trap_handler_\MODE\():
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j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
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// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
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// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
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.4byte s_soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
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.4byte segfault_\MODE\() // 2: reserved
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.4byte m_soft_interrupt_\MODE\() // 3: breakpoint
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.4byte segfault_\MODE\() // 4: reserved
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.4byte s_time_interrupt_\MODE\() // 5: load access fault
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.4byte segfault_\MODE\() // 6: reserved
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.4byte m_time_interrupt_\MODE\() // 7: store access fault
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.4byte segfault_\MODE\() // 8: reserved
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.4byte s_ext_interrupt_\MODE\() // 9: ecall from S-mode
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.4byte segfault_\MODE\() // 10: reserved
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.4byte m_ext_interrupt_\MODE\() // 11: ecall from M-mode
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// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
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j s_soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
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j segfault_\MODE\() // 2: reserved
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j m_soft_interrupt_\MODE\() // 3: breakpoint
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j segfault_\MODE\() // 4: reserved
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j s_time_interrupt_\MODE\() // 5: load access fault
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j segfault_\MODE\() // 6: reserved
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j m_time_interrupt_\MODE\() // 7: store access fault
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j segfault_\MODE\() // 8: reserved
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j s_ext_interrupt_\MODE\() // 9: ecall from S-mode
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j segfault_\MODE\() // 10: reserved
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j m_ext_interrupt_\MODE\() // 11: ecall from M-mode
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// 12 through >=16 are reserved or designated for platform use
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trap_unvectored_\MODE\():
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@ -139,12 +145,34 @@ trap_unvectored_\MODE\():
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addi x6, x6, 8
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addi x16, x16, 8 // update pointers for logging results
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.if (\DEBUG\() == 1) // record extra information (MTVAL, some status bits) about traps
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csrr x1, \MODE\()tval
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sd x1, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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csrr x1, \MODE\()status
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.if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
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li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
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.else
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li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
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.endif
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and x5, x5, x1
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sd x5, 0(x16) // store masked out status bits to the output
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addi x6, x6, 8
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addi x16, x16, 8
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.endif
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// Respond to trap based on cause
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// All interrupts should return after being logged
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csrr x1, \MODE\()cause
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li x5, 0x8000000000000000 // if msb is set, it is an interrupt
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and x5, x5, x1
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bnez x5, trapreturn_\MODE\() // return from interrupt
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// Other trap handling is specified in the vector Table
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csrr x1, \MODE\()cause
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slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
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la x5, exception_vector_table_\MODE\()
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add x5, x5, x1 // compute address of vector in Table
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@ -171,16 +199,16 @@ trapreturn_\MODE\():
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// lw x5, 0(x1) // read the faulting instruction
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// li x1, 3 // check bottom 2 bits of instruction to see if compressed
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// and x5, x5, x1 // mask the other bits
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// beq x5, x1, trapreturn_uncompressed // if 11, the instruction is return_uncompressed
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// beq x5, x1, trapreturn_uncompressed_\MODE\() // if 11, the instruction is return_uncompressed
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// trapreturn_compressed:
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// trapreturn_compressed_\MODE\():
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// csrr x1, mepc // get the mepc again
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// addi x1, x1, 2 // add 2 to find the next instruction
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// j trapreturn_specified // and return
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// j trapreturn_specified_\MODE\() // and return
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// trapreturn_uncompressed:
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// csrr x1, mepc // get the mepc again
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// addi x1, x1, 4 // add 4 to find the next instruction
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// trapreturn_uncompressed_\MODE\():
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// csrr x1, mepc // get the mepc again
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// addi x1, x1, 4 // add 4 to find the next instruction
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trapreturn_specified_\MODE\():
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// reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
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@ -224,6 +252,7 @@ trapreturn_finished_\MODE\():
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csrw \MODE\()epc, x1 // update the epc with address of next instruction
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ld x5, -16(sp) // restore registers from stack before returning
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ld x1, -8(sp)
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csrw \MODE\()ip, 0x0 // clear interrupt pending register to indicate interrupt has been handled
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\MODE\()ret // return from trap
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ecallhandler_\MODE\():
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@ -257,10 +286,14 @@ ecallhandler_changetousermode_\MODE\():
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csrc mstatus, x1
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j trapreturn_\MODE\()
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instrfault_\MODE\():
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ld x1, -8(sp) // load return address int x1 (the address AFTER the jal into faulting page)
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instrpagefault_\MODE\():
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ld x1, -8(sp) // load return address int x1 (the address AFTER the jal to the faulting address)
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j trapreturn_finished_\MODE\() // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
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instrfault_\MODE\():
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ld x1, -8(sp) // load return address int x1 (the address AFTER the jal to the faulting address)
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j trapreturn_finished_\MODE\() // return to the code after recording the mcause
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illegalinstr_\MODE\():
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j trapreturn_\MODE\() // return to the code after recording the mcause
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@ -268,23 +301,63 @@ accessfault_\MODE\():
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// *** What do I have to do here?
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j trapreturn_\MODE\()
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s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compiles, but don't actually do anything yet
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addr_misaligned_\MODE\():
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j trapreturn_\MODE\()
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breakpt_\MODE\():
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j trapreturn_\MODE\()
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s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compiles, but don't actually do anything yet
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li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table.
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sd x5, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
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sw x0, 0(x28)
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j trap_unvectored_\MODE\()
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m_soft_interrupt_\MODE\():
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j trapreturn_\MODE\()
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li x5, 0x7EC
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sd x5, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
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sw x0, 0(x28)
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j trap_unvectored_\MODE\()
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s_time_interrupt_\MODE\():
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j trapreturn_\MODE\()
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li x5, 0x7EC
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sd x5, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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j trap_unvectored_\MODE\()
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m_time_interrupt_\MODE\():
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j trapreturn_\MODE\()
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li x5, 0x7EC
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sd x5, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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j trap_unvectored_\MODE\()
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s_ext_interrupt_\MODE\():
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j trapreturn_\MODE\()
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li x5, 0x7EC
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sd x5, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
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sw x0, 8(x28) // disable the first pin as an output
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sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
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j trap_unvectored_\MODE\()
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m_ext_interrupt_\MODE\():
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j trapreturn_\MODE\()
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li x5, 0x7EC
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sd x5, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
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sw x0, 8(x28) // disable the first pin as an output
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sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
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j trap_unvectored_\MODE\()
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// Table of trap behavior
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@ -294,19 +367,19 @@ m_ext_interrupt_\MODE\():
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.align 3 // aligns this data table to an 8 byte boundary
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exception_vector_table_\MODE\():
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.8byte segfault_\MODE\() // 0: instruction address misaligned
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.8byte addr_misaligned_\MODE\() // 0: instruction address misaligned
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.8byte instrfault_\MODE\() // 1: instruction access fault
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.8byte illegalinstr_\MODE\() // 2: illegal instruction
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.8byte segfault_\MODE\() // 3: breakpoint
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.8byte segfault_\MODE\() // 4: load address misaligned
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.8byte breakpt_\MODE\() // 3: breakpoint
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.8byte addr_misaligned_\MODE\() // 4: load address misaligned
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.8byte accessfault_\MODE\() // 5: load access fault
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.8byte segfault_\MODE\() // 6: store address misaligned
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.8byte addr_misaligned_\MODE\() // 6: store address misaligned
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.8byte accessfault_\MODE\() // 7: store access fault
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.8byte ecallhandler_\MODE\() // 8: ecall from U-mode
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.8byte ecallhandler_\MODE\() // 9: ecall from S-mode
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.8byte segfault_\MODE\() // 10: reserved
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.8byte ecallhandler_\MODE\() // 11: ecall from M-mode
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.8byte instrfault_\MODE\() // 12: instruction page fault
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.8byte instrpagefault_\MODE\() // 12: instruction page fault
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.8byte trapreturn_\MODE\() // 13: load page fault
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.8byte segfault_\MODE\() // 14: reserved
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.8byte trapreturn_\MODE\() // 15: store page fault
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@ -438,7 +511,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
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// they generally do not fault or cause issues as long as these modes are enabled
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// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
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.macro GOTO_M_MODE RETURN_VPN RETURN_PAGETYPE
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.macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
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li a0, 2 // determine trap handler behavior (go to machine mode)
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li a1, \RETURN_VPN // return VPN
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li a2, \RETURN_PAGETYPE // return page types
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@ -446,7 +519,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
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// now in S mode
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.endm
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.macro GOTO_S_MODE RETURN_VPN RETURN_PAGETYPE
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.macro GOTO_S_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
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li a0, 3 // determine trap handler behavior (go to supervisor mode)
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li a1, \RETURN_VPN // return VPN
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li a2, \RETURN_PAGETYPE // return page types
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@ -454,7 +527,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
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// now in S mode
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.endm
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.macro GOTO_U_MODE RETURN_VPN RETURN_PAGETYPE
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.macro GOTO_U_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
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li a0, 4 // determine trap handler behavior (go to user mode)
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li a1, \RETURN_VPN // return VPN
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li a2, \RETURN_PAGETYPE // return page types
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@ -554,6 +627,87 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
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addi x16, x16, 8
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.endm
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// The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
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// This effectively includes everything that isn't to do with page faults (virtual memory)
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.macro CAUSE_INSTR_ADDR_MISALIGNED
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// cause a misaligned address trap
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auipc x28, 0 // get current PC, which is aligned
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addi x28, x28, 0x1 // add 1 to pc to create misaligned address
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jalr x28 // cause instruction address midaligned trap
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.endm
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.macro CAUSE_INSTR_ACCESS
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la x28, 0x0 // address zero is an address with no memory
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jalr x28 // cause instruction access trap
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.endm
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.macro CAUSE_ILLEGAL_INSTR
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.word 0x00000000 // a 32 bit zros is an illegal instruction
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.endm
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.macro CAUSE_BREAKPNT // ****
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ebreak
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.endm
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.macro CAUSE_LOAD_ADDR_MISALIGNED
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auipc x28, 0 // get current PC, which is aligned
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addi x28, x28, 1
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lw x29, 0(x28) // load from a misaligned address
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.endm
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.macro CAUSE_LOAD_ACC
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la x28, 0 // 0 is an address with no memory
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lw x29, 0(x28) // load from unimplemented address
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.endm
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.macro CAUSE_STORE_ADDR_MISALIGNED
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auipc x28, 0 // get current PC, which is aligned
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addi x28, x28, 1
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sw x29, 0(x28) // store to a misaligned address
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.endm
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.macro CAUSE_STORE_ACC
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la x28, 0 // 0 is an address with no memory
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sw x29, 0(x28) // store to unimplemented address
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.endm
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.macro CAUSE_ECALL
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// *** ASSUMES you have already gone to the mode you need to call this from.
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ecall
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.endm
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.macro CAUSE_TIME_INTERRUPT
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// The following code works for both RV32 and RV64.
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// RV64 alone would be easier using double-word adds and stores
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li x28, 0x100 // Desired offset from the present time
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la x29, 0x02004000 // MTIMECMP register in CLINT
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la x30, 0x0200BFF8 // MTIME register in CLINT
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lw x7, 0(x30) // low word of MTIME
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lw x31, 4(x30) // high word of MTIME
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add x28, x7, x28 // add desired offset to the current time
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bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound)
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addi x31, x31, 1 // if wrap, increment most significant word
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sw x31,4(x29) // store into most significant word of MTIMECMP
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nowrap:
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sw x28, 0(x29) // store into least significant word of MTIMECMP
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loop: j loop // wait until interrupt occurs
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.endm
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.macro CAUSE_SOFT_INTERRUPT
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la x28, 0x02000000 // MSIP register in CLINT
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li x29, 1 // 1 in the lsb
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sw x29, 0(x28) // Write MSIP bit
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.endm
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.macro CAUSE_EXT_INTERRUPT
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li x28, 0x10060000 // load base GPIO memory location
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li x29, 0x1
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sw x29, 8(x28) // enable the first pin as an output
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sw x29, 28(x28) // set first pin to high interrupt enable
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sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
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.endm
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.macro END_TESTS
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// invokes one final ecall to return to machine mode then terminates this program, so the output is
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// 0x8: termination called from U mode
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