David Harris
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55e4911cf0
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fdivsqrt code cleanup
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2022-10-09 03:37:27 -07:00 |
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Ross Thompson
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382ccf74a5
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Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS.
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2022-10-05 15:46:53 -05:00 |
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Ross Thompson
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62951ec653
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Fixed wally32e.
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2022-10-05 15:37:01 -05:00 |
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Ross Thompson
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2144343c4a
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Name clarifications.
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2022-10-05 15:36:56 -05:00 |
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Ross Thompson
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2e578eb8d8
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Fixed bug with combined dtim+bus.
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2022-10-05 15:16:01 -05:00 |
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Ross Thompson
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b52ab91028
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Possibly have working dtim + bus config.
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2022-10-05 15:08:20 -05:00 |
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Ross Thompson
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8d01cf32fc
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Updated wavefile.
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2022-10-05 14:55:40 -05:00 |
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Ross Thompson
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a0c5833d6d
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Fixed bug in EBU.
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2022-10-05 14:51:12 -05:00 |
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Ross Thompson
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68aa1434b4
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Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.
Don't use this commit as the rv32i tests are not passing.
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2022-10-05 14:51:02 -05:00 |
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Ross Thompson
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20546857e6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-05 14:03:44 -05:00 |
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David Harris
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f318daa605
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Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests.
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2022-10-05 11:46:52 -07:00 |
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Ross Thompson
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e6b36d0c02
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Optimized the ebu's beat counting.
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2022-10-05 10:58:23 -05:00 |
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Ross Thompson
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9e2cfadd7d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-04 17:39:26 -05:00 |
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Ross Thompson
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c21c71d53d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-04 17:39:14 -05:00 |
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Ross Thompson
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3f59ea6b6d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-04 17:38:49 -05:00 |
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Ross Thompson
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92d7be645b
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Reordered the eviction and fetch in cache so it follows a more logical order.
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2022-10-04 17:36:07 -05:00 |
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Ross Thompson
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8f18bb9243
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Updated constraints file to work with alternate uart.
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2022-10-04 17:35:44 -05:00 |
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Ross Thompson
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52e8e0f5ef
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Modified cache lru to not have the delayed write.
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2022-10-04 15:14:58 -05:00 |
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Kip Macsai-Goren
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d5cd67cf09
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fixed endianness mstatush problem, passes make, not regression
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2022-10-04 17:37:39 +00:00 |
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Kip Macsai-Goren
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2bbcec680f
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addded renamed file
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2022-10-04 17:37:05 +00:00 |
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Kip Macsai-Goren
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c4441eb0fa
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-10-04 17:33:54 +00:00 |
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Kip Macsai-Goren
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175e824a61
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Renamed endianswap to match module name
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2022-10-04 17:33:49 +00:00 |
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Ross Thompson
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56cc04316c
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Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.
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2022-10-02 16:21:21 -05:00 |
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Ross Thompson
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02ed8fc301
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-01 15:01:22 -05:00 |
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Ross Thompson
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bc94f4aef1
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Disable IFU bus access on TrapM.
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2022-10-01 14:54:16 -05:00 |
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Ross Thompson
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e6db1c5cf8
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Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage.
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2022-09-29 18:37:34 -05:00 |
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David Harris
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fc4146f409
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Adding start signals for integer divider to fdivsqrt
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2022-09-29 16:30:25 -07:00 |
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Ross Thompson
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47e936cab3
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Renamed signals in EBU.
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2022-09-29 18:29:38 -05:00 |
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cturek
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c72e2e5d49
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Added integer inputs and flags to divsqrt
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2022-09-29 23:08:27 +00:00 |
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Ross Thompson
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f9c4b32bd5
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Simplification to EBU.
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2022-09-29 18:06:34 -05:00 |
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Ross Thompson
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146ff6ff6a
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Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.
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2022-09-29 11:54:03 -05:00 |
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Ross Thompson
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638e506d0b
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Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
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2022-09-28 17:39:51 -05:00 |
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Ross Thompson
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87485ed237
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Possible fix for ifu/lsu arbiration issue.
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2022-09-27 17:24:35 -05:00 |
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Ross Thompson
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afc6934249
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Possible fix to the bus cache interaction.
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2022-09-27 11:34:33 -05:00 |
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Ross Thompson
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dfe6bdd06d
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Found a hidden bug in the cache to bus fsm interlock.
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2022-09-26 17:41:30 -05:00 |
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Ross Thompson
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f24b0feeed
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renamed ahbmulticontroller to ebu.
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2022-09-26 14:37:18 -05:00 |
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Ross Thompson
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fd47cf05c3
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-26 12:49:16 -05:00 |
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Ross Thompson
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fd2a8e621a
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Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
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2022-09-26 12:48:26 -05:00 |
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Kip Macsai-Goren
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0d2fcaeab1
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added xlen and endianness test edits. xlen passes but endinanness still won't make
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2022-09-26 05:03:19 +00:00 |
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Kip Macsai-Goren
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4fa8b10315
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added simple post processing script to give branch miss proportion in coremark log
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2022-09-26 04:51:04 +00:00 |
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David Harris
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b5d2bbe7ca
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changed always_ff to always in sram1p1rw to fix testbench complaint
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2022-09-25 19:56:40 -07:00 |
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Ross Thompson
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dcc00ef4b3
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Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
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2022-09-23 11:46:53 -05:00 |
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Ross Thompson
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6a6686a34b
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Removed the write first sram model.
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2022-09-22 16:12:08 -05:00 |
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Ross Thompson
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8a6ca027c2
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The valid and dirty bits match the SRAM implementation now.
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2022-09-22 16:09:09 -05:00 |
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Ross Thompson
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29087812e1
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Solved the sram write first / read first issue. Works correctly with read first now.
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2022-09-22 14:16:26 -05:00 |
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Ross Thompson
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f74d21e063
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 18:24:06 -05:00 |
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Ross Thompson
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cd5b8be78f
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Cleaned up the IFU and LSU around dtim and irom address calculation.
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2022-09-21 18:23:56 -05:00 |
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David Harris
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cfa83fdd98
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For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc
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2022-09-21 13:30:35 -07:00 |
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David Harris
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fce927810a
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Fixed testbench-fp to support all again
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2022-09-21 13:19:48 -07:00 |
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David Harris
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f08d5b23d5
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Eliminated store after store stall when no cache; simplified divshiftcalc logic.
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2022-09-21 13:02:34 -07:00 |
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