Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-01 17:34:27 +00:00
Code Issues Packages Projects Releases Wiki Activity
4,520 Commits 4 Branches 2 Tags 53 MiB
540d6c2f41
Commit Graph

4520 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Kip Macsai-Goren
540d6c2f41 added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Ross Thompson
1a9c932157 Renamed SelBusBuffer to SelFetchBuffer. 2022-12-05 17:51:13 -06:00
Ross Thompson
92066f81b6 Removed commented code. 2022-12-05 17:21:56 -06:00
Ross Thompson
4b30712cb2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-05 17:20:12 -06:00
Ross Thompson
37551ecc43 Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags. 2022-12-05 17:19:51 -06:00
rachanaerra
10ff69efc1 updated constraints file 2022-12-05 15:05:21 -06:00
Ross Thompson
dc31add951 Cache signal renames. 2022-12-04 16:09:09 -06:00
Ross Thompson
9bf0eedf73 Optimized way selection logic. 2022-12-04 12:30:56 -06:00
Ross Thompson
a130a96b45 Found possible optimization as the way selection is shared in cache, cacheway, and cachelru. 2022-12-04 01:20:51 -06:00
Ross Thompson
3dea04e644 Moved selectedway mux into cacheway. It makes way more sense there. 2022-12-04 01:15:47 -06:00
Ross Thompson
f557150cae Rename LineByteMux to FetchbufferbyteSel. 2022-12-04 01:00:04 -06:00
Ross Thompson
fc05e27416 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
Ross Thompson
350fdd944d Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." 
This reverts commit fb221d7b64.
 2022-12-04 00:01:58 +00:00
Ross Thompson
87ce09f7d9 Removed old flow directory. 2022-12-03 10:28:39 -06:00
Ross Thompson
45bc732b4d removed imperas-riscv-tests-deleteme 2022-12-03 00:18:42 +00:00
Ross Thompson
d8fdc179f1 removed unusedsrc directory as it was large 384MB! 2022-12-02 17:37:06 -06:00
Ross Thompson
ae4c36936d Removed design ware mult. 2022-12-02 16:51:12 -06:00
cturek
fb221d7b64 Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider. 2022-12-02 21:44:29 +00:00
cturek
04ac350a29 Added flops to preproc 2022-12-02 20:31:08 +00:00
David Harris
3a07d56d33 Renamed FPUStallD to FCvtIntStallD 2022-12-02 11:55:23 -08:00
David Harris
1b0f878c16 Renamed DivStartE to IFDivStartE 2022-12-02 11:30:49 -08:00
David Harris
db5f3c15a4 FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
David Harris
a86c9de36b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-02 04:28:50 -08:00
David Harris
6079a01bc8 update test list 2022-12-02 04:28:47 -08:00
Ross Thompson
602d191580 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 22:36:07 -06:00
David Harris
7c3e8553d1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 16:27:36 -08:00
David Harris
0d23ab3ec1 reorder tests 2022-12-01 16:27:33 -08:00
Ross Thompson
3442b04f9e Properly flush cacheLRU. 2022-12-01 17:32:58 -06:00
David Harris
3a8602523e FPU test list 2022-12-01 10:18:36 -08:00
Ross Thompson
e403800ce8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 11:47:54 -06:00
Ross Thompson
5025664cb0 Removed unused port on cacheway. 2022-12-01 11:47:48 -06:00
David Harris
28996d0b12 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 08:15:51 -08:00
David Harris
1bd639be6d code cleanup 2022-12-01 08:15:48 -08:00
Ross Thompson
e6bd86f4fa Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 17:19:04 -06:00
David Harris
4ddc8fd603 signal sufixes in integer division 2022-11-30 15:15:37 -08:00
Ross Thompson
fa22484cfe Reverted the IROM/DTIM address range modelsim assignment. 2022-11-30 17:13:33 -06:00
Ross Thompson
2f582cd91f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 13:30:37 -06:00
Ross Thompson
a6355b1dcb More optimization. 2022-11-30 11:26:48 -06:00
Ross Thompson
0aa7ce0b24 Removed reset on dirty cache bits. 2022-11-30 11:04:37 -06:00
Ross Thompson
cedb234013 Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now. 2022-11-30 11:01:25 -06:00
Ross Thompson
0454eb95ad Preparing to merge dirty and tag srams. 2022-11-30 10:40:48 -06:00
Ross Thompson
de538d1c2f Intermediate commit. Replaced flip flop dirty bit array with sram. 2022-11-30 00:08:31 -06:00
cturek
10c2d45888 div tests in sim-wally 2022-11-30 02:32:04 +00:00
Ross Thompson
453ea36512 Optimization of cacheway. 2022-11-29 18:30:47 -06:00
Ross Thompson
fbf543bf57 Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault. 2022-11-29 17:19:31 -06:00
Ross Thompson
0277227323 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-29 14:57:38 -06:00
Ross Thompson
b5718c9baa Fixed a bug with the replacement policy. It was updating the wrong set on load hits. 2022-11-29 14:51:09 -06:00
Ross Thompson
96cc4c7ebe Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled. 2022-11-29 14:09:48 -06:00
Kip Macsai-Goren
c7c578c104 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-29 10:43:44 -08:00
Kip Macsai-Goren
44ea8d8b22 added failing satp invalid tests to regression 2022-11-29 10:43:38 -08:00