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1732 Commits

Author SHA1 Message Date
bbracker
b3bc3cf6d0 modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations) 2021-09-04 19:49:26 -04:00
bbracker
c463f177e9 restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair 2021-09-04 19:45:04 -04:00
bbracker
135404174e switching over to hopefully more consistent QEMU simulated clock 2021-09-04 19:43:39 -04:00
bbracker
9fde9f09f2 replace triple gdb breakpoint continue with a double breakpoint ignore in hopes of improving parsing 2021-09-04 19:41:55 -04:00
James E. Stine
02a1fda650 Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR 2021-09-03 10:26:38 -05:00
bbracker
f1a39b467d output trace to linux-testvectors folder 2021-09-01 17:37:46 -04:00
Ross Thompson
2968623f9a Partial multiway set associative icache. 2021-08-30 10:49:24 -05:00
Katherine Parry
70f332fe2f FMA cleanup 2021-08-28 10:53:35 -04:00
Ross Thompson
6a9fa2fae3 Fixed bugs I introduced to the icache. 2021-08-27 15:00:40 -05:00
Ross Thompson
d433db3048 Renamed PCMux (icache) to SelAdr to match dcache. 
Removed unused cache files.
 2021-08-27 11:14:10 -05:00
Ross Thompson
96cbd8e785 Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm. 
One downside is it increases the icache complexity.  However it also fixes an untested bug.  If a region
was uncacheable it would have been possible for the request to be made multiple times.  Now that is
not possible.  Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
 2021-08-27 11:03:36 -05:00
Ross Thompson
4ace7fe946 Renamed ICacheCntrl to icachefsm. 2021-08-26 15:57:17 -05:00
Ross Thompson
d6ff89b7e6 Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits. 2021-08-26 15:43:02 -05:00
Ross Thompson
aea7afead6 Finished moving data path logic from the ICacheCntrl.sv to icache.sv. 2021-08-26 13:06:24 -05:00
Ross Thompson
86fc632790 Moved data path logic from icacheCntrl to icache. 2021-08-26 10:58:19 -05:00
Ross Thompson
fd28c4f556 Removed unused logic in icache. 2021-08-26 10:49:54 -05:00
Ross Thompson
e4bbd3bbc7 Converted the icache type from logic to state type. 2021-08-26 10:41:42 -05:00
Ross Thompson
91fba80a6d Additional cleanup of ahblite. 2021-08-25 22:53:20 -05:00
Ross Thompson
8836d91896 Removed amo logic from ahblite. Removed many unused signals from ahblite. 2021-08-25 22:45:13 -05:00
Ross Thompson
596bc138bc Forgot to include a few files in the last few commits. 
Also reorganized the dcache by read cpu path, write cpu path, and bus interface path.
Changed i/o names on subwordread to match signals in dcache.
 2021-08-25 22:30:05 -05:00
Ross Thompson
0530047f53 Moved dcache fsm to separate module. 2021-08-25 21:37:10 -05:00
Ross Thompson
d23b860c96 Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory. 
This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
 2021-08-25 21:09:42 -05:00
Ross Thompson
c5e2443298 Replaced dcache generate ORing with or_rows. 2021-08-25 13:46:36 -05:00
Ross Thompson
e5336f4ee1 Rename of DCacheMem to cacheway. 
simplified dcache names.
 2021-08-25 13:33:15 -05:00
Ross Thompson
e9a1dc90f6 Removed generate around the dcache memories. 2021-08-25 13:27:26 -05:00
Ross Thompson
2ccf479354 Moved more logic inside the dcache memory. 2021-08-25 13:17:07 -05:00
Ross Thompson
35e57a7c61 partial dcache reorg. 2021-08-25 12:42:05 -05:00
Ross Thompson
983524e81b Updated linux test bench documenation and scripts. 2021-08-25 10:54:47 -05:00
David Harris
7d24ed3c51 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-08-25 06:47:20 -04:00
David Harris
3fa55a01f4 simplified or_rows generation and renamed oneHotDecoder to onehotdecoder 2021-08-25 06:46:41 -04:00
Ross Thompson
fe378f2692 Added function tracking to linux test bench. 2021-08-24 11:08:46 -05:00
Ross Thompson
0cc47f3daf Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage. 2021-08-23 15:46:17 -05:00
Ross Thompson
c31b7b4dc5 Wally previously was overcounting retired instructions when they were flushed. 
InstrValidM was used to control when the counter was updated.  However this is
not suppress the counter when the instruction is flushed in the M stage.
 2021-08-23 12:24:03 -05:00
Ross Thompson
9fdcc6c9ca Renamed output of qemu trace. 2021-08-22 22:56:34 -05:00
Ross Thompson
2825074114 Confirmed David's changes to the interrupt code. 
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine.  This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege.  Since the CPU
is currently in machine mode the interrupt must be taken if MIE.

Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
 2021-08-22 21:36:31 -05:00
David Harris
4677b4bb38 possible interrupt code 2021-08-22 17:02:40 -04:00
Ross Thompson
ddbc659d7b Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do. 2021-08-19 10:33:11 -05:00
Ross Thompson
65870877c3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-17 16:06:54 -05:00
Ross Thompson
91b51c698e Minor changes to dcache. 2021-08-17 15:22:10 -05:00
Katherine Parry
c8847b27e8 all conversions go through the execute stage result mux 2021-08-16 13:06:09 -04:00
Ross Thompson
a70d51f4c9 Modified the hptw's simulation error message so that synthesis does not attempt to include this statement. 2021-08-16 10:02:29 -05:00
Ross Thompson
36761d9155 Fixed syntax errors in some floating point modules. This came up in 
Xilinx synthesis.
 2021-08-15 16:48:49 -05:00
Ross Thompson
6c57002d0e Added logic to linux test bench to not stop simulation on csr write faults. 2021-08-15 11:13:32 -05:00
Ross Thompson
af2c6fd6ff Updated linux-wave.do to have cursors at the timer interrupt problem. 2021-08-13 17:29:37 -05:00
Ross Thompson
766c829d31 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-13 17:23:04 -05:00
Ross Thompson
55fda4de62 Switched ExceptionM to dcache to be just exceptions. 
Added test bench logic to hold forces until the W stage is unstalled.
 2021-08-13 15:53:50 -05:00
Ross Thompson
32db21659f Fixed bugs with CSR checking. The parsing algorithm was messing up the token order after the CSR token. 2021-08-13 14:53:43 -05:00
Ross Thompson
e141a00934 Cleaned up the linux testbench by removing old code and signals. 
Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
 2021-08-13 14:39:05 -05:00
Katherine Parry
aedd71d570 move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
Ross Thompson
6a6d5e9b15 Added documentation about how the dcache and ptw interact. 2021-08-12 18:05:36 -05:00
Ross Thompson
814fd80b0f Optimized subwordread to reduce critical path from 8 muxes to 5 muxes + 1 AND gate. 2021-08-12 13:36:33 -05:00
Ross Thompson
9ff9c4dff9 Minor cleanup of the linux test bench. 2021-08-12 11:14:55 -05:00
Ross Thompson
565c01709d Removed unused states from dcache fsm. 2021-08-11 17:06:09 -05:00
Ross Thompson
2be625d8b9 Modified invalid plic reads to return 0 rather than deadbeaf. 2021-08-11 16:56:22 -05:00
Ross Thompson
4b25fed6d8 Simplified Dcache by sharing the read data mux with the victim selection mux. 2021-08-11 16:55:55 -05:00
Ross Thompson
22f274c51e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-10 13:36:29 -05:00
Ross Thompson
67c1028862 Dcache and LSU clean up. 2021-08-10 13:36:21 -05:00
Katherine Parry
e00f181bcf LZA added to FMA and attemting a merged FMA and adder in synthesis 2021-08-10 13:57:16 -04:00
Ross Thompson
cce0571925 Fixed another bug with the atomic instrucitons implemention in the dcache. 2021-08-08 22:50:31 -05:00
Ross Thompson
d3be04b7de Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the 
cache's SRAM would occur.  Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
 2021-08-08 11:42:10 -05:00
Ross Thompson
fc7016eea6 Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. 
Fixed logic for trace update in the M and W stages.  The M stage should not update if there
is an instruction fault.
 2021-08-08 00:28:18 -05:00
Ross Thompson
aa9a5d879b Finally past the CLINT issues. 2021-08-06 16:41:34 -05:00
Ross Thompson
0bfbcef8ab Now past the CLINT issues. 2021-08-06 16:16:39 -05:00
Ross Thompson
9be10cdc8b Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts. 2021-08-06 16:06:50 -05:00
Ross Thompson
c749d08542 fixed the read timer issue but we still have problems with interrupts and i/o devices. 2021-08-06 10:16:06 -05:00
Ross Thompson
3582be4dbb Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction. 2021-08-05 16:49:03 -05:00
Ross Thompson
37ba6b19e5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-30 17:57:13 -05:00
Ross Thompson
f808b29065 Added some comments to linux testbench. 2021-07-30 17:57:03 -05:00
Ross Thompson
e166cc84ee Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files. 2021-07-30 14:24:50 -05:00
Ross Thompson
74fba4bb06 Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
Ross Thompson
7b9e53fbe5 Removed 1 cycle delay on store miss. 
Changed some logic to partially support atomics.
 2021-07-30 14:00:51 -05:00
Ross Thompson
d8878581f4 Created new linux test bench and parsing scripts. 2021-07-29 20:26:50 -05:00
Katherine Parry
d60e394ef9 all fpu units use the unpacking unit 2021-07-28 23:49:21 -04:00
Ross Thompson
915d8136e5 Fixed bug which caused stores to take an extra clock cycle. 2021-07-26 12:22:53 -05:00
Ross Thompson
79ebc53977 Fixed bug with the compressed immediate generation. Several formats should zero extend. 2021-07-26 11:55:31 -05:00
Ross Thompson
ef55b30e99 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
 2021-07-26 11:55:00 -05:00
Ross Thompson
60177b92a6 Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation. 2021-07-25 23:14:28 -05:00
Katherine Parry
30ac22edff fixed some fpu lint errors 2021-07-24 16:41:12 -04:00
Katherine Parry
6c4aa624a5 fpu cleanup 2021-07-24 15:00:56 -04:00
Katherine Parry
ef28679721 fpu cleanup 2021-07-24 14:59:57 -04:00
Kip Macsai-Goren
3008111bcd added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet 2021-07-23 16:02:42 -04:00
Kip Macsai-Goren
381a93b45b added sfence to legal instructions, zeroed out rom file to populate for tests 2021-07-23 15:55:08 -04:00
Kip Macsai-Goren
da9ead2d95 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-23 15:16:01 -04:00
bbracker
b093bf84a4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-23 14:00:52 -04:00
bbracker
0e64b99dc0 testbench workaround for QEMU's SSTATUS XLEN bits 2021-07-23 14:00:44 -04:00
kipmacsaigoren
f3579032bd Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's 2021-07-23 11:57:58 -05:00
David Harris
5d2b30e332 Removed LEVELx states from HPTW 2021-07-23 08:11:15 -04:00
Ross Thompson
9939c66a1f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 19:42:32 -05:00
Ross Thompson
3e916da36e Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. 
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage.  Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM.  At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data.  When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
 2021-07-22 19:42:19 -05:00
Kip Macsai-Goren
52faa22774 include SFENCE.VMA in legal instructions 2021-07-22 20:24:24 -04:00
David Harris
98660e0d19 Minor unpacking cleanup 2021-07-22 17:52:37 -04:00
Ross Thompson
551e3491af Moved the ReadDataW register into the datapath. 
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
 2021-07-22 14:52:03 -05:00
Ross Thompson
fbbfc799b9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 14:05:08 -05:00
Ross Thompson
9c90b4bdf7 Fixed bug with the itlb fault not dcache ptw ready state to ready state. 2021-07-22 14:04:56 -05:00
David Harris
c9890afb7f Move Z sign swapping out of unpacker 2021-07-22 14:32:38 -04:00
David Harris
31be570461 Move Z=0 mux out of unpacker. 2021-07-22 14:28:55 -04:00
David Harris
63718cef8f Move Z=0 mux out of unpacker. 2021-07-22 14:22:28 -04:00
David Harris
21a65f45cd Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken. 2021-07-22 14:18:27 -04:00
David Harris
b53eb6d030 Simplify unpacker 2021-07-22 13:42:16 -04:00
David Harris
19dac66264 Simplify unpacker 2021-07-22 13:40:42 -04:00
David Harris
44141047ef Removed Assumed1 from FPU interface 2021-07-22 13:04:47 -04:00
David Harris
3ad2170ffd Simplified interface to fclassify and fsgn (fixed) 2021-07-22 12:33:38 -04:00
David Harris
5e155e4fd1 Simplified interface to fclassify and fsgn 2021-07-22 12:30:46 -04:00
Ross Thompson
b4029a2848 Cleaned up icache and dcache. 2021-07-22 11:06:44 -05:00
Ross Thompson
3dd89a7e62 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 10:38:24 -05:00
Ross Thompson
25a8920a69 Tested all numbers of ways for dcache 1, 2, 4, and 8. 2021-07-22 10:38:07 -05:00
bbracker
d3059dd04c fix UART RX FIFO bug where tail pointer can overtake head pointer 2021-07-22 02:09:41 -04:00
bbracker
57a2917997 make address translator signals visible in waveview 2021-07-21 20:07:49 -04:00
bbracker
cca16cc5b4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-21 20:07:03 -04:00
bbracker
6e460c5032 replace physical address checking with virtual address checking because address translator is broken 2021-07-21 19:47:13 -04:00
bbracker
25391bcfce hardcoded hack to fix missing STVEC vector 2021-07-21 19:34:57 -04:00
Ross Thompson
dac93bb366 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
c69a5dc8a6 fixed issue with tlbflush remaining high during a stalled sfence instruction 2021-07-21 17:43:36 -04:00
Ross Thompson
71375ba655 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 16:39:07 -05:00
Ross Thompson
7785401281 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 14:56:30 -05:00
Ross Thompson
313bc5255c Improved address bus names and usages in the walker, dcache, and tlbs. 
Merge branch 'walkerEnhance' into main
 2021-07-21 14:55:09 -05:00
Ross Thompson
310b454fa1 Added comment about better muxing. 2021-07-21 14:40:14 -05:00
Ross Thompson
5860f147d4 4 way set associative is now working. 2021-07-21 14:01:14 -05:00
Kip Macsai-Goren
4eaf95de60 Fixed TLB parameterization and valid bit flop to correctly do instr page faults 2021-07-21 14:44:43 -04:00
Katherine Parry
01f0b4e5df FDIV and FSQRT work 2021-07-21 14:08:14 -04:00
bbracker
f9c0d33773 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-21 13:04:11 -04:00
bbracker
82ce85c24f progress on recovering from QEMU's errors 2021-07-21 13:00:32 -04:00
Ross Thompson
e0990535e1 Fixed remaining bugs in 2 way set associative dcache. 2021-07-21 10:35:23 -05:00
Ross Thompson
3f780f012a Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux. 
Also forgot to include cacheLRU.sv file.
 2021-07-20 23:17:42 -05:00
Katherine Parry
b9081e514c FMA parameterized 2021-07-20 22:04:21 -04:00
Ross Thompson
14e949d6e3 Partially working 2 way set associative d cache. 2021-07-20 17:51:42 -05:00
bbracker
f9b6bd91f5 fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk 2021-07-20 17:55:44 -04:00
bbracker
a02694a529 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 15:04:13 -04:00
bbracker
a3823ce3a9 commented out old hack that used hardcoded addresses 2021-07-20 15:03:55 -04:00
David Harris
e5e3f5abe6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 14:46:58 -04:00
David Harris
1f3dfa20f6 flag for optional boottim 2021-07-20 14:46:37 -04:00
Ross Thompson
4c785845f3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-20 13:27:58 -05:00
Ross Thompson
00081ebc68 Replaced FinalReadDataM with ReadDataM in dcache. 2021-07-20 13:27:29 -05:00
bbracker
6b72b1f859 ignore mhpmcounters because QEMU doesn't implement them 2021-07-20 13:37:52 -04:00
bbracker
a1ea654b11 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 12:08:46 -04:00
David Harris
e1a1a8395e Parameterized I$/D$ configurations and added sanity check assertions in testbench 2021-07-20 08:57:13 -04:00
bbracker
077662bfa1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 05:40:49 -04:00
bbracker
9e658466e6 testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr) 2021-07-20 05:40:39 -04:00
James E. Stine
12e09a7ace slight mod to fpdiv - still bug in batch vs. non-batch 2021-07-20 01:47:46 -04:00
bbracker
3b10ea9785 major fixes to CSR checking 2021-07-20 00:22:07 -04:00
Ross Thompson
365485bd8b Added performance counters for dcache access and dcache miss. 2021-07-19 22:12:20 -05:00
Ross Thompson
508c3e35af Restored TIM range. 2021-07-19 21:17:31 -05:00
bbracker
99fa2bbbc3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 19:30:40 -04:00
bbracker
cb15d7e4c7 change debugBuildroot because GDB formatted list is now 50 lines long per instruction (we lost 6 CSRs on the whole) 2021-07-19 19:30:29 -04:00
David Harris
23b76a724d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 18:19:59 -04:00
David Harris
4d40b5faef Added cache configuration to config files 2021-07-19 18:19:46 -04:00
bbracker
c1d63fe77c MemRWM shouldn't factor into PCD checking 2021-07-19 18:03:30 -04:00
bbracker
4d10cfc98b create qemu_output.txt 2021-07-19 18:02:41 -04:00
bbracker
c8203c171e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 17:11:49 -04:00
bbracker
f7d040af1e make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways 2021-07-19 17:11:42 -04:00
Kip Macsai-Goren
5880cbafe4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 16:46:46 -04:00
bbracker
1aeef4e7d1 remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux 2021-07-19 16:22:05 -04:00
bbracker
bc5222e721 put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests 2021-07-19 16:19:24 -04:00
bbracker
65df5c087b adapt testbench to removal of ReadDataWEn signal 2021-07-19 15:42:14 -04:00
bbracker
ae5663a244 adapt testbench to removal of signal 2021-07-19 15:41:50 -04:00
bbracker
64e0fe4c5a whoops MTIMECMP is always 64 bits 2021-07-19 15:40:53 -04:00
bbracker
bdb1ece183 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 15:13:14 -04:00
bbracker
cd469035be make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset 2021-07-19 15:13:03 -04:00
Kip Macsai-Goren
2614df627e added changes to priority encoders from synthesis branch (correctly this time I hope) 2021-07-19 15:06:14 -04:00
Ross Thompson
bf3ca50a9a Furture simplification of the dcache ReadDataW update. 2021-07-19 12:46:31 -05:00
Ross Thompson
9f76e1d64d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-19 12:32:35 -05:00
Ross Thompson
b61dad4b83 Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW. 2021-07-19 12:32:16 -05:00
bbracker
1b0b9d0f79 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 13:21:04 -04:00
bbracker
f31a0ded75 change buildroot expectations to match reality 2021-07-19 13:20:53 -04:00
Ross Thompson
4d53b9002f Broken. 
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated.  This leads to incorrect index
selection in the dcache.
 2021-07-19 10:33:27 -05:00
bbracker
67eb1f5c6b change sram1rw to have a small delay so that we don't have signals changing on clock edges 2021-07-19 11:30:07 -04:00
David Harris
2ed6285a3d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 10:34:18 -04:00
James Stine
7d571f27a6 delete sbtm_a4 and sbtm_a5 as they are not needed 2021-07-19 08:06:00 -05:00
James Stine
186b5dee69 remove sbtm3.sv - not needed 2021-07-19 08:00:53 -05:00
James Stine
5b1f9797f5 update part I on sbtm change 2021-07-19 07:59:27 -05:00
David Harris
8e01007d1c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 00:25:06 -04:00
Katherine Parry
c9180f4ebd FDIV and FSQRT passes when simulating in modelsim 2021-07-18 23:00:04 -04:00
bbracker
e4a50a5bb8 change memread testvectors to not left-shift bytes and half-words 2021-07-18 21:49:53 -04:00
David Harris
46ab609498 Updated FMA1 with parameterized size 2021-07-18 20:40:49 -04:00
bbracker
5e9dcb3f1c linux testbench progress 2021-07-18 18:47:40 -04:00
David Harris
ed64d37e65 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-18 17:36:29 -04:00
David Harris
4f8f52f283 Added FLEN, NE, NF to config and started using these in FMA1 2021-07-18 17:28:25 -04:00
Katherine Parry
60dabb9094 fdivsqrt inegrated, but not completley working 2021-07-18 14:03:37 -04:00
David Harris
8317be5aed Renamed pagetablewalker to hptw 2021-07-18 04:11:33 -04:00
David Harris
c75d70126f LSUArb: Removed Demuxes on ReadDataW, DataMiisalignedM, HPTWStall 2021-07-18 03:51:30 -04:00
David Harris
3f7a3b280e HPTW: Simpliifieid PRegEn 2021-07-18 03:35:38 -04:00
David Harris
60bd27a40e Removed EndWalk signal and simplified TLBMissReg 2021-07-18 03:26:43 -04:00
Ross Thompson
14220684b6 Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue. 2021-07-17 21:02:24 -05:00
Ross Thompson
009c5314b4 Fixed LRSC in 64bit version. 32bit version is broken. 2021-07-17 20:58:49 -05:00
David Harris
8bdf1eaf0f added lrsc.sv 2021-07-17 21:15:08 -04:00
David Harris
8d348dacce Started atomics 2021-07-17 21:11:41 -04:00
David Harris
574f7d9c32 moved subwordread to lsu 2021-07-17 20:37:20 -04:00
David Harris
e82374d19f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-17 20:01:23 -04:00
David Harris
9a86fc899b LSU cleanup 2021-07-17 20:01:03 -04:00
David Harris
d9750c16a5 Pushing HPTWPAdrM flop into LSUArb 2021-07-17 19:39:18 -04:00
David Harris
586341a41a Simplified VPN case statement 2021-07-17 19:34:01 -04:00
Ross Thompson
9cfbc4aec0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-17 18:27:44 -05:00
David Harris
35b7577be2 Finished HPTW TranslationPAdr simlification 2021-07-17 19:27:24 -04:00
Ross Thompson
1aac97030a Before returning to the ready state the dcache must set SelAdr = 0 on the cycle before. 2021-07-17 18:26:29 -05:00
David Harris
2b1fdfbae2 Further TranslationVAdr simplification 2021-07-17 19:24:37 -04:00
David Harris
b785a20f90 Continued Translation Address Cleanup of TranslationPAdrMux 2021-07-17 19:16:56 -04:00
David Harris
fc88b3a693 Continued Translation Address Cleanup 2021-07-17 19:09:13 -04:00
David Harris
6536ef8dce Refining address interface between HPTW and LSU 2021-07-17 19:02:18 -04:00
David Harris
7b92e7e590 Fixed bad register in I-FSD-01 Imperas test. 2021-07-17 17:08:07 -04:00
David Harris
a67292b5f3 trap.sv comment cleanup 2021-07-17 16:01:07 -04:00
David Harris
c1c3249709 trap.sv cleanup 2021-07-17 15:57:10 -04:00
David Harris
af5e1f7f39 Finished removing PageTableEntry redundant signals from hptw 2021-07-17 15:50:52 -04:00
David Harris
e182cac9bc hptw: Removed NonBusTrapM from LSU 2021-07-17 15:24:26 -04:00
David Harris
2f81e4c70d hptw: Removed NonBusTrapM from LSU 2021-07-17 15:22:24 -04:00
David Harris
428a9c1ca3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-17 15:11:43 -04:00
David Harris
863e6e72d6 hptw: Propagating PageTableEntryF removal through IFU 2021-07-17 15:04:39 -04:00
David Harris
a855e0170e hptw: Propagating PageTableEntryF removal through LSU 2021-07-17 15:01:01 -04:00
bbracker
8d65d50085 separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
David Harris
d4eeabe355 hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE 2021-07-17 14:48:44 -04:00
bbracker
82fc766819 swapped out linux testbench signal names 2021-07-17 14:48:12 -04:00
bbracker
18fb282a37 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-17 14:46:38 -04:00
bbracker
4a3503281f swapped out linux testbench signal names 2021-07-17 14:46:18 -04:00
David Harris
86e04c080d hptw: Added ValidLeaf and ValidNonLeaf for readability, renamed _WDV to _READ states 2021-07-17 14:36:27 -04:00
David Harris
714eef4a1a hptw: Eliminated A and D bit faults while walking page table, per spec 2021-07-17 14:29:20 -04:00
David Harris
90c5312f85 hptw: Simplified TranslationVAdr calculation based just on DTLBWalk 2021-07-17 14:16:33 -04:00
David Harris
42aee1db30 hptw: renamed DTLBMissQ to DTLBWalk 2021-07-17 14:13:00 -04:00
David Harris
6f22e9a393 hptw: renamed ADRE to ADR 2021-07-17 14:02:59 -04:00
David Harris
3ce22a60b3 hptw: replaced PreviousWalkerState with a PageType FSM 2021-07-17 13:54:58 -04:00
David Harris
89fd653cc1 hptw: removed ITLBMissFQ 2021-07-17 13:44:08 -04:00
David Harris
87aa527de7 hptw: minor cleanup 2021-07-17 13:40:12 -04:00
David Harris
ea2aa469a1 hptw: Simplifed out AnyTLBMiss 2021-07-17 12:07:51 -04:00
David Harris
784e6cf538 hptw: Renamed Memstore to MemWrite 2021-07-17 12:01:43 -04:00
David Harris
0a6622a6fb hptw: Merged RV32/64 FSMs 2021-07-17 11:55:24 -04:00
David Harris
cf0975c937 hptw: FSM simplification 2021-07-17 11:41:43 -04:00
David Harris
4469b5a4b3 hptw: default state should be unreachable 2021-07-17 11:33:16 -04:00
David Harris
9cee6c2281 hptw: factored Misaligned 2021-07-17 11:31:16 -04:00
David Harris
fa12727bbb hptw: factored HPTWRead 2021-07-17 11:25:59 -04:00
David Harris
708f8cc3a2 hptw: factored HPTWRead 2021-07-17 11:25:52 -04:00
David Harris
ef63e1ab52 hptw: factored pregen 2021-07-17 11:11:10 -04:00
David Harris
880aa1c03a HPTW: more cleanup 2021-07-17 04:55:01 -04:00
David Harris
a0f6c9aec1 HPTW: factored out DTLBWrite/ITLBWrite 2021-07-17 04:44:23 -04:00
David Harris
08e494dd7d HPTW: factored out PageTableENtry 2021-07-17 04:40:01 -04:00
David Harris
bd270acdb6 more cleaning up FSM 2021-07-17 04:35:51 -04:00
David Harris
6d8a6eeba0 cleaning up FSM 2021-07-17 04:26:41 -04:00
David Harris
330e500442 Simplify FSM 2021-07-17 04:12:31 -04:00
David Harris
03ef3f7f17 Pulled TranslationPAdr mux out of HPTW FSM 2021-07-17 04:06:26 -04:00
David Harris
5698433463 Simplified bad PTE detection 2021-07-17 03:30:17 -04:00
David Harris
ac67342dd4 Pulled out shared PTEReg 2021-07-17 03:21:09 -04:00
David Harris
86ca9abe42 Flip-flop clean-up 2021-07-17 03:15:47 -04:00
David Harris
9a15a2f7df Flip-flop clean-up 2021-07-17 03:12:24 -04:00
David Harris
8241dd4599 Flip-flop clean-up 2021-07-17 03:10:17 -04:00
David Harris
a8a5fa4b3c Started pagetablewalker cleanup: combined state flops shared for both RV versions 2021-07-17 02:53:52 -04:00
David Harris
b65788d165 Replaced separate PageTypeF and PageTypeM with common PageType 2021-07-17 02:31:23 -04:00
David Harris
dac22d5016 Removed more unused signals from ahblite 2021-07-17 02:21:54 -04:00
David Harris
a898bbb991 Removed rest of HRDATAW from ahblite 2021-07-17 02:15:24 -04:00
David Harris
a19d3f126f Commented out HRDATAW logic in ebu 2021-07-17 02:10:57 -04:00
David Harris
e3dc59c5a2 renamed or_rows.sv 2021-07-16 20:17:03 -04:00
David Harris
1bd5c137a6 Reduced size of physical memory by 16 for performance 2021-07-16 20:10:12 -04:00
Kip Macsai-Goren
d10fd25c33 included virtual memory tests in testbench 2021-07-16 17:57:24 -04:00
Ross Thompson
0b3dc288ec Made furture progress in the mmu tests. 2021-07-16 15:56:06 -05:00
Ross Thompson
5e18a15a4c Added guide for Ben to do linux conversion. 2021-07-16 15:04:30 -05:00
Ross Thompson
6521d2b468 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
1aabee0478 Updated the config so the tim has a bigger range. 2021-07-16 12:35:00 -05:00
Ross Thompson
b3bf04d474 Updated wave file. 2021-07-16 12:34:37 -05:00
Ross Thompson
46bce70e42 Fixed walker fault interaction with dcache. 2021-07-16 12:22:13 -05:00
bbracker
b0fcfc2773 reduce number of UART ports to 1 2021-07-16 12:42:29 -04:00
bbracker
01ca22af49 changed stop of linux boot from arch_cpu_idle to do_idle 2021-07-16 12:27:15 -04:00
Ross Thompson
e0f719d513 Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues. 2021-07-16 11:12:57 -05:00
bbracker
ae7d48c326 incremental linux config de-bloating 2021-07-16 12:08:58 -04:00
bbracker
40352ab7e4 incremental linux config de-bloating 2021-07-16 11:33:11 -04:00
bbracker
b1fe4ff295 incremental linux config de-bloating 2021-07-16 11:15:25 -04:00
bbracker
f34e28d187 incremental linux config de-bloating 2021-07-16 01:58:21 -04:00
bbracker
3bcc5808d4 incremental linux config de-bloating 2021-07-16 01:54:36 -04:00
bbracker
ff90e6744c incremental linux config de-bloating 2021-07-16 01:43:16 -04:00
bbracker
ca5a1755f3 incremental linux config de-bloating 2021-07-16 01:33:51 -04:00
bbracker
b003c651be incremental linux config de-bloating 2021-07-16 01:25:41 -04:00
bbracker
ae886b015d incremental linux config de-bloating 2021-07-16 01:00:12 -04:00
bbracker
7340e089f7 incremental linux config de-bloating 2021-07-16 00:46:22 -04:00
bbracker
c4716af4d6 incremental linux config de-bloating 2021-07-16 00:41:18 -04:00
bbracker
0238b869fb incremental linux config de-bloating 2021-07-16 00:34:41 -04:00
bbracker
3273b030e1 incremental linux config de-bloating 2021-07-16 00:16:12 -04:00
bbracker
66bf2005fe incremental linux config de-bloating 2021-07-16 00:10:31 -04:00
bbracker
4734f0eee5 incremental linux config de-bloating 2021-07-15 23:53:15 -04:00
bbracker
e565adfece incremental linux config de-bloating 2021-07-15 23:30:24 -04:00
bbracker
3ff723493f incremental linux config de-bloating 2021-07-15 23:12:21 -04:00
bbracker
8586462ee5 incremental linux config de-bloating 2021-07-15 23:00:20 -04:00
bbracker
03e0bdaa5a incremental linux config de-bloating 2021-07-15 21:33:52 -04:00
bbracker
e922732fc5 incremental linux config de-bloating 2021-07-15 20:54:36 -04:00
bbracker
c2535308fd working linux config 2021-07-15 18:49:54 -04:00
Kip Macsai-Goren
abd5b1c02d Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction. 2021-07-15 18:30:29 -04:00
bbracker
3b6291b734 stripped down busybox a bit 2021-07-15 16:07:56 -04:00
Ross Thompson
e5d624c1fa Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
fd1de6b047 Updated wave file. 2021-07-15 11:04:49 -05:00
Ross Thompson
b9902b0560 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. 2021-07-15 11:00:42 -05:00
Ross Thompson
8610ef204c Renamed DCacheStall to LSUStall in hart and hazard. 
Added missing logic in lsu.
 2021-07-15 10:16:16 -05:00
Ross Thompson
704f4f724e dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
ba1e1ec231 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
c74d26eea4 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
c79650b508 Added d cache StallW checks for any time the cache wants to go to STATE_READY. 2021-07-14 17:25:50 -05:00
Ross Thompson
2c946a282f Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Katherine Parry
f5bfdf46db fpu unpacking unit created 2021-07-14 17:56:49 -04:00
Ross Thompson
e91501985c Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
adce800041 Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled. 2021-07-14 15:47:38 -05:00
Ross Thompson
d78e31e9df Forgot to include one hot decoder. 2021-07-14 15:46:52 -05:00
Ross Thompson
f4295ff097 Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts. 
This solves the committedM issue.
 2021-07-14 15:00:33 -05:00
bbracker
335afb14e7 testvector unlinker for dev purposes 2021-07-14 11:05:34 -04:00
James Stine
e6d19be87c put back for now to test fdiv 2021-07-14 06:48:29 -05:00
bbracker
46e704b7ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-14 00:21:39 -04:00
bbracker
92899b33f8 make testvector scripts agree with new file structure; use symbols to determine end of linux boot 2021-07-14 00:21:29 -04:00
Ross Thompson
9b756d6a94 Implemented uncached reads. 2021-07-13 23:03:09 -05:00
Ross Thompson
e8bf502bc2 Added CommitedM to data cache output. 2021-07-13 22:43:42 -05:00
bbracker
28887bb3d5 needed to create a directory for gdb script 2021-07-13 19:39:57 -04:00
Ross Thompson
3e57c899a2 Partially working changes to support uncached memory access. Not sure what CommitedM is. 2021-07-13 17:24:59 -05:00
James E. Stine
46001fef27 mod 2 of fpdivsqrt update 2021-07-13 16:59:17 -04:00
James E. Stine
8382a17969 Update fpdivsqrt item until move into uarch 2021-07-13 16:53:20 -04:00
bbracker
f2bf4920d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 16:16:04 -04:00
bbracker
64d22753b5 changed QEMU to use different ports 2021-07-13 16:15:51 -04:00
Ross Thompson
baa2b5d15f Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled. 2021-07-13 14:51:42 -05:00
Ross Thompson
3c1a717399 Fixed the fetch buffer accidental overwrite on eviction. 2021-07-13 14:21:29 -05:00
Ross Thompson
32f27cfecf Dcache AHB address generation was wrong. Needed to zero the offset. 2021-07-13 14:19:04 -05:00
Ross Thompson
afc1bc9c38 Moved StoreStall into the hazard unit instead of in the d cache. 2021-07-13 13:20:50 -05:00
David Harris
9de97c1e20 Fixed busybear by restoring InstrValidW needed by testbench 2021-07-13 14:17:36 -04:00
Ross Thompson
47e16f5629 Fixed back to back store issue. 
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
 2021-07-13 12:46:20 -05:00
David Harris
2ba82d1a5c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:26:51 -04:00
David Harris
223086ac33 added or.sv 2021-07-13 13:26:40 -04:00
Katherine Parry
ca19b2e215 Fixed writting MStatus FS bits 2021-07-13 13:22:04 -04:00
Katherine Parry
efdec72df1 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
David Harris
93d6688c3c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:19:24 -04:00
David Harris
b5dddec858 Fixed InstrValid from W to M stage for CSR performance counters 2021-07-13 13:19:13 -04:00
bbracker
3565580f40 updated buildroot make procedure to incorporate configs more robustly 2021-07-13 12:40:14 -04:00
Ross Thompson
224e3b2991 Fixed subword write. subword read should not feed into subword write. 2021-07-13 11:21:44 -05:00
Ross Thompson
30b7c4436c restored rv64ic config back to full sized dtim. 2021-07-13 11:18:54 -05:00
Ross Thompson
3951eb56f5 Modularized the shadow memory to reduce performance hit. 2021-07-13 10:55:57 -05:00
Ross Thompson
e594eb540d Got the shadow ram cache flush working. 2021-07-13 10:03:47 -05:00
bbracker
99587f58f7 whoops I accidentally made main.config into a symbolic link; now it is a source file 2021-07-13 11:00:01 -04:00
bbracker
fab906821a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 10:04:13 -04:00
bbracker
4b615c1564 working config for a buildroot that boots 2021-07-13 10:04:09 -04:00
David Harris
861ef5e1cb Replaced .or with or_rows structural code in MMU read circuitry for synthesis. 2021-07-13 09:32:02 -04:00
Ross Thompson
49f6eec579 Team work on solving the dcache data inconsistency problem. 2021-07-12 23:46:32 -05:00
Ross Thompson
ecc9b5006e Now updates the dtim with the dirty data in the dcache. 
Simulation is showing issues.  It lookslike the cache is not
evicting the correct data.
 2021-07-12 15:13:27 -05:00
Ross Thompson
1cc258ade1 Progress towards the test bench flush. 2021-07-12 14:22:13 -05:00
Katherine Parry
f3ac46df86 fcvt.sv cleanup 2021-07-11 21:30:01 -04:00
Katherine Parry
36f59f3c99 Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
bbracker
6bd0ca673c rootfs.cpio no longer overlaps 2021-07-11 05:11:12 -04:00
Ross Thompson
f26d635614 Fixed the spurious AHB requests to address 0. Somehow by not having a default 
(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
 2021-07-10 22:34:47 -05:00
Ross Thompson
fed7042fd9 Loads are working. 
There is a bug when the icache stalls 1 cycle before the d cache.
 2021-07-10 22:15:44 -05:00
Ross Thompson
60ed023734 Actually writes the correct data now on stores. 2021-07-10 17:48:47 -05:00
Ross Thompson
efe37ea079 Write miss with eviction works. 2021-07-10 15:17:40 -05:00
Ross Thompson
d65c01bc29 Write Hits and Write Misses without eviction are working correctly! The next 
step is to add eviction of dirty lines.
 2021-07-10 10:56:25 -05:00
bbracker
feaeeaf6ac greatly stripped down unused stuff in linux config 2021-07-10 11:53:35 -04:00
David Harris
20f2a4e47c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 19:18:35 -04:00
David Harris
d3ab6b192a added missing tlbmixer.sv 2021-07-09 19:18:23 -04:00
bbracker
3be73695e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 18:56:28 -04:00
bbracker
2a54f6f242 fix_mem.py bugfix 2021-07-09 18:56:17 -04:00
Ross Thompson
b1ceeb40df Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address. 
I think this is do to the cycle latency of stores.  We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
 2021-07-09 17:14:54 -05:00
bbracker
1f52a2f938 organize/update buildroot scripts for new image 2021-07-09 17:03:47 -04:00
Ross Thompson
4c0cee1c19 Design loads in modelsim, but trap is an X. 2021-07-09 15:37:16 -05:00
Ross Thompson
ec80cc1820 Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented. 
Also faults and the dcache ptw interlock are not implemented.
 2021-07-09 15:16:38 -05:00
David Harris
39bd7e7edc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 07:53:30 -04:00