116 Commits

Author	SHA1	Message	Date
David Harris	5142bfd624	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-23 06:15:49 -07:00
David Harris	3407b63c8a	Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.	2021-10-23 06:15:26 -07:00
James E. Stine	a60e19dc3f	Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking	2021-10-22 13:41:50 -05:00
Katherine Parry	00cc1e0c5c	put the FMA priority encoders into their own module	2021-10-22 10:03:12 -07:00
James E. Stine	0e0a107a98	Get rid of lint warning - still need more testing though	2021-10-21 15:19:22 -05:00
James E. Stine	49721a169b	Clean up some FPU and add pipelined fpdivsqrt to fpu.sv	2021-10-21 13:52:12 -05:00
James E. Stine	129ef03b2d	Fix fpdivsqrt lint error on CPA for convergence	2021-10-20 17:46:13 -05:00
James E. Stine	7536e0a2ee	Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.	2021-10-20 12:00:41 -05:00
Katherine Parry	33e5a078bf	cvtfp module documented	2021-10-14 15:25:31 -07:00
James E. Stine	6b30adb309	Clean up some signals - beautification onging	2021-10-14 17:12:00 -05:00
James E. Stine	eb64a7f0c9	Update to fpdivsqrt to go on posedge as it should. Also an update to ... individual regression test for TestFloat (still needs some tweaking)	2021-10-13 17:14:42 -05:00
Katherine Parry	09f51871c5	lint warnings fixed	2021-10-12 09:45:02 -07:00
Katherine Parry	4ea56ac68b	some fpu lint warnings fixed - still working on it	2021-10-11 18:32:03 -07:00
bbracker	8eff03bf1a	simplify flopenrc's that didn't actually need to be flopenrc's	2021-10-10 12:25:05 -07:00
Katherine Parry	44b023ace1	FMA matches diagram and lint warnings fixed	2021-10-09 17:38:10 -07:00
kipmacsaigoren	086e6d130a	rename adder in fpu for synthesis	2021-10-08 17:47:54 -05:00
James E. Stine	b90d7b8083	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
David Harris	1f6e4c71fc	Modified rxfull determination in UART, started division	2021-09-12 20:00:24 -04:00
Ross Thompson	3b12235954	Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.	2021-09-11 15:40:27 -05:00
Katherine Parry	7607adc951	FMA cleanup	2021-08-28 10:53:35 -04:00
Katherine Parry	facd4062d0	all conversions go through the execute stage result mux	2021-08-16 13:06:09 -04:00
Katherine Parry	567260751a	move some FPU select muxs to execute stage	2021-08-13 14:41:22 -04:00
Katherine Parry	21555c392f	LZA added to FMA and attemting a merged FMA and adder in synthesis	2021-08-10 13:57:16 -04:00
Katherine Parry	d8ca70fc45	all fpu units use the unpacking unit	2021-07-28 23:49:21 -04:00
Katherine Parry	8198e8162a	fixed some fpu lint errors	2021-07-24 16:41:12 -04:00
Katherine Parry	85d240c2a5	fpu cleanup	2021-07-24 15:00:56 -04:00
Katherine Parry	67ab0b165c	fpu cleanup	2021-07-24 14:59:57 -04:00
David Harris	427063ee05	Minor unpacking cleanup	2021-07-22 17:52:37 -04:00
David Harris	0822d46e97	Move Z sign swapping out of unpacker	2021-07-22 14:32:38 -04:00
David Harris	85aaa4c6d7	Move Z=0 mux out of unpacker.	2021-07-22 14:28:55 -04:00
David Harris	c04f40d6e5	Move Z=0 mux out of unpacker.	2021-07-22 14:22:28 -04:00
David Harris	625d925369	Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken.	2021-07-22 14:18:27 -04:00
David Harris	f4b45adf44	Simplify unpacker	2021-07-22 13:42:16 -04:00
David Harris	02f0c67e6f	Simplify unpacker	2021-07-22 13:40:42 -04:00
David Harris	2f23ca2b77	Removed Assumed1 from FPU interface	2021-07-22 13:04:47 -04:00
David Harris	926ffc8a15	Simplified interface to fclassify and fsgn (fixed)	2021-07-22 12:33:38 -04:00
David Harris	ae29eaa98d	Simplified interface to fclassify and fsgn	2021-07-22 12:30:46 -04:00
Katherine Parry	59f79722ab	FDIV and FSQRT work	2021-07-21 14:08:14 -04:00
Katherine Parry	61f81bb76e	FMA parameterized	2021-07-20 22:04:21 -04:00
James E. Stine	b36d6fe1be	slight mod to fpdiv - still bug in batch vs. non-batch	2021-07-20 01:47:46 -04:00
David Harris	1b55f584c7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 10:34:18 -04:00
James Stine	62b4ef6953	delete sbtm_a4 and sbtm_a5 as they are not needed	2021-07-19 08:06:00 -05:00
James Stine	892bc68918	remove sbtm3.sv - not needed	2021-07-19 08:00:53 -05:00
James Stine	55f2720f89	update part I on sbtm change	2021-07-19 07:59:27 -05:00
David Harris	0c41b8102d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 00:25:06 -04:00
Katherine Parry	8d101548f1	FDIV and FSQRT passes when simulating in modelsim	2021-07-18 23:00:04 -04:00
David Harris	4729a72167	Updated FMA1 with parameterized size	2021-07-18 20:40:49 -04:00
David Harris	398e9583e9	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-18 17:36:29 -04:00
David Harris	f22b6e7397	Added FLEN, NE, NF to config and started using these in FMA1	2021-07-18 17:28:25 -04:00
Katherine Parry	3527620c0b	fdivsqrt inegrated, but not completley working	2021-07-18 14:03:37 -04:00