Ross Thompson
2d1cb0c3a3
Reordered inputs/outputs in caches.
2022-01-03 22:52:50 -06:00
Ross Thompson
ff24718c28
Added generate around the spill logic so it is only used if supporting compressed instructions.
2022-01-03 22:23:04 -06:00
Ross Thompson
120a9d6a58
Minor improvement to icache.
2022-01-03 22:00:35 -06:00
Ross Thompson
89f4b920ff
More Icache clean up.
2022-01-03 21:22:34 -06:00
Ross Thompson
2f7cb82c72
Major icache cleanup.
2022-01-03 21:12:17 -06:00
Ross Thompson
8c7638688b
The ifu now directly supports compressed without the icache providing the implemenation.
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The icache still constains all the orignal muxing logic to handle spills. This should be removed.
2022-01-03 20:49:47 -06:00
Ross Thompson
324362eee5
Almost working compressed instructions with compressed detection and processing in ifu rather than icache.
2022-01-03 18:10:15 -06:00
Ross Thompson
82fbc502e0
Prepared the ifu and icache for moving spills to ifu.
2022-01-03 17:09:36 -06:00
Ross Thompson
c501276067
Fixed a bug where the instruction fetch got out of sync with the icache.
2022-01-03 13:27:15 -06:00
David Harris
95407a6ea7
Replaced && and || with & and | in non-fp files per new style guidelines
2022-01-02 21:47:21 +00:00
Ross Thompson
7055bfa4a7
Added mux to select between uncache instruction requests and cached instructions requests.
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Cacheless design almost works with the exception of compressed instructions.
2021-12-30 18:09:37 -06:00
Ross Thompson
89dc598a83
Patched up the linux-wave.do file.
2021-12-30 17:53:43 -06:00
Ross Thompson
89303579ee
Progress on non dcache mode working.
2021-12-30 15:51:07 -06:00
Ross Thompson
bd531d1996
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-30 14:56:24 -06:00
Ross Thompson
59a38e3efd
Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.
2021-12-30 14:56:17 -06:00
David Harris
451f37729f
Added names to generate blocks
2021-12-30 20:55:48 +00:00
Ross Thompson
9ea308b2d7
icache separated from bus fetch fsm. Does not work yet.
2021-12-30 14:23:05 -06:00
Ross Thompson
3803b9cd2d
Changed names of Icache signals.
2021-12-30 11:01:11 -06:00
Ross Thompson
8d5c86e908
More name cleanup in caches.
2021-12-30 09:18:16 -06:00
Ross Thompson
c2b0e61466
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
Ross Thompson
0a7dc96052
Fixed complex bug where FENCE is instruction class miss predicted as a taken branch.
2021-12-21 11:29:28 -06:00
Ross Thompson
b0507b96b0
Identified bug in the IFU which selects PCNextF when InvalidateICacheM is true. If the ID is invalid PCNextF should NOT be PCE.
2021-12-20 23:45:55 -06:00
Ross Thompson
53736096a6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
9adcf86a40
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
...
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
79ec4161b6
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
David Harris
3a9071e509
Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
2021-12-15 12:10:45 -08:00
David Harris
f4957fdac1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
Ross Thompson
45b38ea9fe
Comments for dcache and icache refactoring.
2021-12-14 14:46:29 -06:00
kwan
e4f214090d
.* resolved in ifu.sv
2021-12-02 10:32:35 -08:00
kwan
2a77bc8053
.* in ifu/ifu.sv eliminated
2021-12-02 09:45:55 -08:00
Ross Thompson
2f85ac7f38
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
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If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
koooo142857
0a33b0904d
aligned all files in ifu folder
2021-10-27 12:43:55 -07:00
David Harris
106982e493
more lsu/ifu lint cleanup
2021-10-23 12:10:13 -07:00
David Harris
8b1dc81d34
more lsu/ifu lint cleanup
2021-10-23 12:00:32 -07:00
David Harris
88b2d9e687
lsu/ifu lint cleanup
2021-10-23 11:41:20 -07:00
David Harris
708b914a65
Lint cleanup from wallypipeliendhart
2021-10-23 10:29:52 -07:00
David Harris
817795f619
Lint cleanup: ahblite, ifu, hart
2021-10-23 10:12:33 -07:00
Ross Thompson
b92070a67a
Updated Dcache to fully support flush. This appears to work.
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Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
2021-09-17 10:25:21 -05:00
Ross Thompson
eb7b5f1d63
Added invalidate to icache.
2021-09-16 16:15:54 -05:00
David Harris
72c1cc33f5
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
Ross Thompson
1e88784bd4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
bb8ec549a7
fixed issue with tlbflush remaining high during a stalled sfence instruction
2021-07-21 17:43:36 -04:00
Ross Thompson
6ccbdc372d
Broken.
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Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
David Harris
e55546da34
hptw: Propagating PageTableEntryF removal through IFU
2021-07-17 15:04:39 -04:00
David Harris
fe8910437a
Replaced separate PageTypeF and PageTypeM with common PageType
2021-07-17 02:31:23 -04:00
Ross Thompson
96aa106852
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
2021-07-15 11:56:35 -05:00
Ross Thompson
4549a9f1c9
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
278bbfbe3c
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
Ross Thompson
6041aef263
completed read miss branch through dcache fsm.
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The challenge now is to connect to ahb and lsu.
2021-07-08 17:53:08 -05:00
David Harris
78850bfcd8
MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
2021-07-06 15:29:42 -04:00
