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Author SHA1 Message Date
Jordan Carlin
527304ca62 Attempt to fix buildroot makefile 2024-07-25 22:26:34 -07:00
Jordan Carlin
2e0dca3f28 Move verilator stack limit to setup.sh/csh insteaed of site-setup 2024-07-25 21:35:52 -07:00
Jordan Carlin
e78fac1624 Replace /opt/riscv after merge 2024-07-25 21:33:31 -07:00
Jordan Carlin
2f1a101735 Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-07-25 21:21:57 -07:00
Jordan Carlin
22a7ba1889 Cleanup 2024-07-25 21:16:00 -07:00
Jacob Pease
8a5898ebc1 Added carriage returns to line feed characters. UART messages print properly now. 2024-07-25 13:05:57 -05:00
Jacob Pease
f12319ca96 Changed formatting and added new UART divsor calculation from OpenSBI. 2024-07-25 13:04:27 -05:00
Rose Thompson
957de2e988 Merge pull request #896 from davidharrishmc/dev 
Updated ImperasTG derived config to turn off peripherals
 2024-07-25 12:20:31 -05:00
David Harris
cf08d954e1 Updated ImperasTG derived config to turn off peripherals 2024-07-25 10:08:34 -07:00
Rose Thompson
2e4ca4c876 Merge pull request #895 from davidharrishmc/dev 
Fix Issue 894 about floating-point decoding of reserved rm/frm
 2024-07-25 11:51:32 -05:00
David Harris
7360be1234 Legalized PMPconfig WARL 2024-07-25 09:43:54 -07:00
David Harris
c637e40058 CHeck legal rnum field when decoding aes64ks1i 2024-07-25 09:19:23 -07:00
Jacob Pease
6fc10adc25 Added ability to split boot.memfile into boot.mem and data.mem. 2024-07-25 11:19:15 -05:00
David Harris
7234abebef Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt 2024-07-25 09:09:13 -07:00
David Harris
337e40ac1b Issue #894: trap on floating-point ops with reserved rounding modes 2024-07-25 06:59:58 -07:00
Jacob Pease
02bb9b0b8b Fixed SDCCLK name discrepency. 2024-07-24 22:48:31 -05:00
Jacob Pease
a34836c08b Commented out references to old axi IP from wally.tcl. 2024-07-24 22:47:15 -05:00
Jacob Pease
ffec8cfb20 Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram. 2024-07-24 22:46:24 -05:00
Jacob Pease
36d330a173 Masked lower byte when writing to DLL. 2024-07-24 22:44:27 -05:00
Jacob Pease
a97c7f0b58 Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future 2024-07-24 22:43:47 -05:00
Jacob Pease
e175a41863 Added uart header to gpt.c. 2024-07-24 22:43:16 -05:00
Jordan Carlin
308deba1fb Linux readme updates 2024-07-24 20:19:30 -07:00
Jordan Carlin
204fd2e9ff Update buildroot makefile to test for write access to $RISCV and remove separate sudo/no_sudo versions (just run the makefile as sudo if needed) 2024-07-24 20:19:30 -07:00
Jordan Carlin
6d77b22281 Automatically determine number of threads to use in wally-tool-chain-install 2024-07-24 20:19:30 -07:00
Jordan Carlin
602d126776 Build nproc linux 2024-07-24 20:19:30 -07:00
Jordan Carlin
c8519ce54f Build testvectors with buildroot 2024-07-24 20:19:30 -07:00
Jordan Carlin
04b8739756 Add cpio to installation for buildroot 2024-07-24 19:55:18 -07:00
David Harris
5ac02c79c6 Merge pull request #892 from ross144/main 
Adds synthesizable RVVI FPGA hardware
 2024-07-24 12:21:36 -07:00
Rose Thompson
5a6e32576d Fixed the reset bug in wallyTracer. 2024-07-24 13:32:46 -05:00
Rose Thompson
994386f12c Removed unused file. 2024-07-24 13:30:25 -05:00
Rose Thompson
9053923d92 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-07-24 13:14:25 -05:00
Rose Thompson
13db14db6b Factored out the rvvi testbench code into rvvitbwrapper. 2024-07-24 13:10:57 -05:00
Rose Thompson
c11036358a Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. 2024-07-24 12:47:50 -05:00
Rose Thompson
fb1869fcb9 Updated verilog-ethernet to remove all verilator warnings or at least suppress them. 2024-07-24 10:13:03 -05:00
Jordan Carlin
07ac498623 Switch to logger function and fix exit codes 2024-07-23 23:42:03 -07:00
Jordan Carlin
4c0265f67d Update logging grep 2024-07-23 23:40:42 -07:00
Jordan Carlin
76277d1e7d Fix logging 2024-07-23 23:40:03 -07:00
Jordan Carlin
790f566eaa Remove hardcoded /opt/riscv 2024-07-23 23:29:45 -07:00
Rose Thompson
7960f26e84 Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings. 2024-07-23 17:44:37 -05:00
Rose Thompson
35efbd6a54 Changes are confirmed to work on the FPGA. 2024-07-23 17:39:38 -05:00
Jacob Pease
c18b3d814d Fixed verilog bugs. 2024-07-23 17:26:39 -05:00
Jacob Pease
23d9c7a486 Fixed syntax bugs. inline functions are now static and in the spi.h header. 2024-07-23 17:00:32 -05:00
Rose Thompson
bfb3b63a24 Code cleanup. 2024-07-23 16:35:05 -05:00
Jacob Pease
692bbc35fd Initial pass on SPI based bootloader code finished. 2024-07-23 16:33:49 -05:00
Jacob Pease
659f0d3646 Added some minor error checking to gpt.c. 2024-07-23 16:32:52 -05:00
Jacob Pease
fe0f6de2ab Added sd_read64 to help with block reads and crc checking. 2024-07-23 16:32:29 -05:00
Rose Thompson
fe9ac36928 Fixed rvvi csr counting. 2024-07-23 16:22:23 -05:00
Rose Thompson
da2511c63c Fixed bugs in the rvvi synth logic which encoded csr instructions. 2024-07-23 16:16:11 -05:00
Jacob Pease
a95106b516 Progress made on implementing new disk read function. 2024-07-23 15:47:23 -05:00
Jacob Pease
db13ed63b9 Removed references to card_type. 2024-07-23 15:46:18 -05:00