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2,099 Commits 5 Branches 2 Tags 53 MiB
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552 Commits

Author SHA1 Message Date
Skylar Litz
546f7fb4c2 fix some interrupt timing bugs 2021-12-03 12:32:38 -08:00
Ross Thompson
500e6ff430 Fixed buildroot to work with the fpga's merge. 2021-12-02 18:09:43 -06:00
Ross Thompson
b03ca464f1 Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
Ross Thompson
a871118116 Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
5642918ead Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
bbracker
fed0bb08d6 UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses 2021-11-25 11:01:59 -08:00
bbracker
cffb72042a activate STVAL for buildroot 2021-11-21 10:40:28 -08:00
David Harris
82cfebfb83 Coremark Cleanup, trying compile from addins 2021-11-19 06:09:04 -08:00
David Harris
690410721d Cleaning up CoreMark benchmark 2021-11-18 20:12:52 -08:00
David Harris
8e8b84f532 vert "Simplifying riscv-coremark" 
This reverts commit ce8232e396.
 2021-11-18 18:40:13 -08:00
David Harris
ce8232e396 Simplifying riscv-coremark 2021-11-18 17:15:40 -08:00
David Harris
402b473dbb CoreMark testing 2021-11-18 16:14:25 -08:00
David Harris
0a281a06e0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:28:33 -08:00
Skylar Litz
6fde97b16c fixed interrupt timing bug 2021-11-16 16:46:17 -08:00
David Harris
c610be25a7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-16 12:30:55 -08:00
bbracker
2203590f9f get current privilege level from GDB for checkpoints 2021-11-15 14:49:00 -08:00
Ross Thompson
7497422667 Changed several things. 
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
 2021-11-12 11:13:50 -06:00
Skylar Litz
3dd83b3113 fix timing of delayed interrupt 2021-11-11 09:35:51 -08:00
David Harris
570f24a9e4 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
bbracker
c92d41a597 checkpoint MIDELEG support 2021-11-06 03:44:23 -07:00
bbracker
bc6332a780 fix merge conflict 2021-11-05 23:42:15 -07:00
bbracker
17e776f853 checkpoints now use binary ram files 2021-11-05 22:37:05 -07:00
bbracker
0c7681b942 fix testbench interrupt timing 2021-11-02 21:19:12 -07:00
David Harris
d7f0abca5a Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
dda035891a PIPELINE test running 2021-11-01 12:44:35 -07:00
David Harris
60573b92b2 Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
David Harris
360930fe8b Fixed exe2memfile parsing of weird line in arch64d test 2021-10-30 07:26:18 -07:00
David Harris
247f247ad3 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
7df4b0c8e7 commented out some failing FPU tests 2021-10-27 11:27:34 -07:00
David Harris
582c2bf37b Fixed FResultSelM to select proper flags 2021-10-27 11:02:42 -07:00
David Harris
5783e47e1a Changes for floating point sims 2021-10-27 10:37:35 -07:00
David Harris
90cf37b881 commented out nonworking tests 2021-10-26 08:56:49 -07:00
David Harris
67adc1d7d5 removed referenc outputs 2021-10-26 08:51:49 -07:00
bbracker
66e53929ce adapt testbench linux to use reset_ext 2021-10-25 13:26:44 -07:00
bbracker
39efadf2cf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
bbracker
8c4e6baf48 change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros 2021-10-25 12:25:32 -07:00
Ross Thompson
32f0b97cd3 Updated uncore to use sdc. 
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
 2021-10-25 14:07:44 -05:00
David Harris
2bf51362e2 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
bbracker
9b98a499d7 some linux testbench cleanup 2021-10-25 10:04:30 -07:00
bbracker
046a78a8fc manually resolved git merge conflicts in testbench linux after checkpointing 2021-10-24 15:02:19 -07:00
bbracker
36b39358c6 add checkpointing to linux testbench 2021-10-24 06:47:35 -07:00
bbracker
26eead1c77 add W stage signals to linux testbench 2021-10-23 14:00:53 -07:00
bbracker
de6a52f6eb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 13:17:37 -07:00
bbracker
3c0b0987d2 add option for regression to do a partial execution of buildroot 2021-10-23 13:17:30 -07:00
David Harris
2cfbd888fd more lsu/ifu lint cleanup 2021-10-23 12:00:32 -07:00
David Harris
e2e950ac0f Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
4c480a40f6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3249d65209 Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
Ross Thompson
77e2b6f9a9 Merge branch 'main' into fpga 2021-10-22 16:09:16 -05:00
Katherine Parry
7c7c0f538a put the FMA priority encoders into their own module 2021-10-22 10:03:12 -07:00