Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.

wally-pipelined/regression/lint-wally

@@ -4,7 +4,7 @@
 export PATH=$PATH:/usr/local/bin/
 verilator=`which verilator`
 
-basepath=$(dirname $0)
+basepath=$(dirname $0)/..
 for config in rv64g rv32g; do
     echo "$config linting..."
     if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv --relative-includes); then

wally-pipelined/regression/regression-wally.py

@@ -35,7 +35,7 @@ configs = [
     ),
     TestCase(
         name="lints",
-        cmd="../lint-wally &> {}",
+        cmd="./lint-wally &> {}",
         grepstr="All lints run with no errors or warnings"
     ),
 ]

wally-pipelined/regression/wally-pipelined-batch.do

@@ -32,7 +32,7 @@ vlib work_${1}_${2}
 
 # default to config/rv64ic, but allow this to be overridden at the command line.  For example:
 # do wally-pipelined-batch.do ../config/rv32ic rv32ic
-vlog -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv -suppress 2583
+vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv -suppress 2583
 
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals

wally-pipelined/regression/wally-pipelined.do

@@ -37,7 +37,7 @@ vlib work
 #}
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
-vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv -suppress 2583
+vlog -lint +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv -suppress 2583
 vopt +acc work.testbench -G TEST=$2 -o workopt 
 vsim workopt
 

wally-pipelined/src/fpu/cla52.sv

@@ -215,6 +215,7 @@ module cla_sub52 (S, X, Y);
    wire 	 LOGIC0;
    wire 	 CIN;
    wire 	 CO_52;
+   wire   CO_64;
    
    assign Bbar = ~B;
    assign LOGIC0 = 0;

wally-pipelined/src/fpu/divconv_pipe.sv

@@ -65,6 +65,8 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r
    logic [59:0] 	d2, n2;   
    logic [11:0] 	d3;   
 
+   logic muxr_out, cout1, cout2, cout3, cout4, cout5, cout6, cout7;
+
    // Check if exponent is odd for sqrt
    // If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA
    assign d2 = (exp_odd&op_type) ? {vss,d,6'h0} : {d,7'h0};

wally-pipelined/testbench/testbench.sv

@@ -27,7 +27,7 @@
 `include "wally-config.vh"
 `include "tests.vh"
 
-module testbench ();
+module testbench;
   parameter TESTSPERIPH = 0; // set to 0 for regression
   parameter TESTSPRIV = 0; // set to 0 for regression
   parameter DEBUG=0;
@@ -331,7 +331,7 @@ logic [3:0] dummy;
   
 endmodule
 
-module riscvassertions();
+module riscvassertions;
   // Legal number of PMP entries are 0, 16, or 64
   initial begin
     assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");