8 Commits

Author	SHA1	Message	Date
Jordan Carlin	022b98a64b	Update all iterative makes to use	2024-09-29 23:14:19 -07:00
Rose Thompson	8248f2dd66	Added MAXSDCCLOCK to parameters set by the FPGA makefile.	2024-09-03 10:55:15 -07:00
Rose Thompson	9471ccd2fc	Updated Makefiles and source files to build the zsbl according to the config.	2024-09-02 14:03:47 -07:00
Rose Thompson	2e55f1cecc	Well on the way to a fully automated FPGA build process which ... correctly sets the clocks and memory locations.	2024-09-02 11:19:02 -07:00
Jordan Carlin	564ce83e11	Update linker scripts to avoid hardcoded /opt/riscv	2024-08-09 20:15:28 -07:00
Jacob Pease	336a413f31	Added ability to split boot.memfile into boot.mem and data.mem.	2024-07-25 11:19:15 -05:00
Jacob Pease	7a417d7a6c	Added true bootloader to fpga/zsbl directory.	2024-05-31 15:28:25 -05:00
Rose Thompson	60f96112db	Moved the zero stage boot loader to the fpga directory.	2024-03-01 10:23:55 -06:00