Ross Thompson
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47638cdccf
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Looks like rdtime was accidentally replaced with rrame from a find and replace.
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2021-12-20 21:26:38 -06:00 |
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Ross Thompson
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d830721a11
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Fixed Type 5b interaction between dcache and hptw.
This is a load concurrent with ITLBMiss.
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2021-12-20 18:33:31 -06:00 |
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Ross Thompson
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6aff6b0fa3
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Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM.
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2021-12-20 10:03:56 -06:00 |
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Ross Thompson
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53736096a6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-20 10:03:19 -06:00 |
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Ross Thompson
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b261b18aa8
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More signal name cleanup in LSU.
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2021-12-19 22:47:48 -06:00 |
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Ross Thompson
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533c2f3556
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Remove verbosity from lsu state machine.
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2021-12-19 22:41:34 -06:00 |
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Ross Thompson
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82dd41a0fd
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Rename of SelPTW to SelHPTW.
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2021-12-19 22:24:07 -06:00 |
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Ross Thompson
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9c2fc30507
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Signal renames.
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2021-12-19 22:21:03 -06:00 |
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Ross Thompson
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2f5de7eb82
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Hardware reductions in the lsu.
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2021-12-19 22:00:28 -06:00 |
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Ross Thompson
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035ce99938
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Removed HPTWStall. Not needed as InterlockStall from the LSU provides the equivalent.
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2021-12-19 21:36:54 -06:00 |
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Ross Thompson
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30770db4ac
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Removed lsuArb and placed remaining logic in lsu.sv.
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
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2021-12-19 21:34:40 -06:00 |
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Ross Thompson
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019e300a14
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Added file showing how to compile riscv toolchain for different extension combinations.
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2021-12-19 20:31:55 -06:00 |
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Ross Thompson
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db76878581
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Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card.
mv qemu patches to tests directory.
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2021-12-19 20:11:32 -06:00 |
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David Harris
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193885c958
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Moved generate of conditional units to hart
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2021-12-19 17:03:57 -08:00 |
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David Harris
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1196e5c191
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Moved generate statements for optional units into wallypipelinedhart
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2021-12-19 16:53:41 -08:00 |
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Ross Thompson
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7b2f5440a5
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Changes to buildroot to support MemAdrM to IEUAdrM name changes.
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2021-12-19 18:24:40 -06:00 |
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Ross Thompson
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aeb8c94df1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-19 18:16:49 -06:00 |
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Ross Thompson
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cef4b6399d
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Switched to using an always block for lsu stall logic. This avoids the problematic x propagation.
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2021-12-19 18:16:08 -06:00 |
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Ross Thompson
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814bcec7b7
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Implemented what I think is the last required change for the lsu state machine.
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2021-12-19 17:57:12 -06:00 |
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Ross Thompson
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54fd8678b0
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Created hack to get around imperas64mmu unknown (value = x) bug.
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2021-12-19 17:53:13 -06:00 |
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Ross Thompson
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13f0e9bafa
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Fixed bug where icache did not replay PCF on itlb miss.
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2021-12-19 17:01:13 -06:00 |
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Ross Thompson
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04d0b85f96
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Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
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2021-12-19 16:12:31 -06:00 |
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David Harris
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5e1c3e322b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-19 13:53:53 -08:00 |
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David Harris
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691c1c0dd0
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ALUControl cleanup
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2021-12-19 13:53:45 -08:00 |
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Katherine Parry
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ece9e9df84
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fixed some small errors in FMA
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2021-12-19 13:51:46 -08:00 |
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Ross Thompson
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202203904c
|
Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm.
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2021-12-19 15:10:33 -06:00 |
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Ross Thompson
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9adcf86a40
|
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
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2021-12-19 14:57:42 -06:00 |
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Ross Thompson
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0257c08641
|
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
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2021-12-19 14:00:30 -06:00 |
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Ross Thompson
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620f4a58d4
|
Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states.
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2021-12-19 13:55:57 -06:00 |
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Ross Thompson
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fdf493bd47
|
minro change. comments about needed changes in dcache.
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2021-12-19 13:53:02 -06:00 |
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David Harris
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c04c56dae1
|
Renamed zero to eq in flag generation
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2021-12-19 11:49:15 -08:00 |
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David Harris
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e5d2d7a3fd
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Controller fix
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2021-12-18 22:08:23 -08:00 |
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David Harris
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8a597390e0
|
Renamed RD1D to R1D, etc.
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2021-12-18 21:26:00 -08:00 |
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David Harris
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7fb4213751
|
Simplified shifter right input
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2021-12-18 10:25:40 -08:00 |
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Ross Thompson
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f601b3ae53
|
Merge branch 'tlb_fixes' into main
|
2021-12-18 12:24:17 -06:00 |
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David Harris
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d97d34ee32
|
Simplified Shifter Right input
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2021-12-18 10:21:17 -08:00 |
|
David Harris
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852c521328
|
Shared ALU mux input for shifts
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2021-12-18 10:08:52 -08:00 |
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David Harris
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a7d7f852a6
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Factored out common parts of shifter
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2021-12-18 10:01:12 -08:00 |
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David Harris
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7868c0da55
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Cleaning shifter
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2021-12-18 09:43:09 -08:00 |
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David Harris
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b453454b24
|
Moved W64 truncation after result mux
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2021-12-18 09:27:25 -08:00 |
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David Harris
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2a5a7eff82
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Forwarding logic factoring
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2021-12-18 05:40:38 -08:00 |
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David Harris
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1212e21eba
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Simplified FWriteInt interfaces by merging into RegWrite
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2021-12-18 05:36:32 -08:00 |
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David Harris
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da1df17fbb
|
Do File cleanups
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2021-12-17 17:45:26 -08:00 |
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Ross Thompson
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2f86e84843
|
Merge remote-tracking branch 'origin/tlb_fixes' into main
|
2021-12-17 14:40:29 -06:00 |
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Ross Thompson
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79ec4161b6
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Added more debugging code for FPGA.
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2021-12-17 14:40:25 -06:00 |
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Ross Thompson
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5264577dcf
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Possible fix for icache deadlock interaction with hptw.
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2021-12-17 14:38:25 -06:00 |
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David Harris
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7a8162497b
|
Added irscv-arch-test and rsicv-isa-sim
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2021-12-15 12:38:35 -08:00 |
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David Harris
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3a9071e509
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Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
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2021-12-15 12:10:45 -08:00 |
|
David Harris
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f0059b7b3a
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IEU cleanup:
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2021-12-15 11:38:26 -08:00 |
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Ross Thompson
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9f798250ea
|
Oups missed files in the last commit.
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2021-12-15 10:25:08 -06:00 |
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