Madeleine Masser-Frye
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374dfd1fc2
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added 'd' suffix to muxes for data-critical synths
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2022-06-10 21:11:05 +00:00 |
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DTowersM
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a61d1ab087
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simplified coremark
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2022-06-10 19:15:17 +00:00 |
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DTowersM
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b586e3af37
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added some comments to help debuggers in the future
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2022-06-10 01:44:52 +00:00 |
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slmnemo
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5ac17eca1d
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Passed Regression: Seems to work perfectly fine
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2022-06-09 18:21:13 -07:00 |
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slmnemo
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75dffe4dcc
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Merge branch 'main' into cacheburstmode
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2022-06-09 17:51:03 -07:00 |
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slmnemo
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a4c7d1d936
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?
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2022-06-09 17:50:47 -07:00 |
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DTowersM
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d280f10a8d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-10 00:38:07 +00:00 |
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DTowersM
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4e5d7ec3d6
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changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
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2022-06-10 00:37:53 +00:00 |
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slmnemo
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c4bc608268
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Changes made on 9th Jun
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2022-06-09 17:33:51 -07:00 |
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slmnemo
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cc8acd947d
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Fixed lint error
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2022-06-09 17:22:04 -07:00 |
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David Harris
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c1a40a15dd
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New RAM for further testing
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2022-06-09 23:50:43 +00:00 |
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stineje
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d3ad512d3c
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Update integer division for r4 and qslc_r4a2.c
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2022-06-09 16:45:13 -05:00 |
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David Harris
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5612ca7041
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qslc_r4a2 generator
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2022-06-09 17:26:47 +00:00 |
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slmnemo
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8ae57f075f
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Fixed error when doing uncached accesses where HTRANS was always 2
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2022-06-08 18:58:07 -07:00 |
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slmnemo
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1605544bfc
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Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.
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2022-06-08 17:34:02 -07:00 |
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Madeleine Masser-Frye
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88285c684c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-09 00:08:15 +00:00 |
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Madeleine Masser-Frye
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f50b3837f5
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restored functionality of makeCoefTable()
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2022-06-09 00:07:51 +00:00 |
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Madeleine Masser-Frye
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a54837b102
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added one bit muxes for data critical synths
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2022-06-09 00:06:12 +00:00 |
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Madeleine Masser-Frye
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fbd384680e
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added false path for data critical muxes
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2022-06-09 00:05:38 +00:00 |
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slmnemo
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655266a216
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Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending
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2022-06-08 15:59:15 -07:00 |
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slmnemo
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a64e65e54c
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Fixed ifu displaying LSU bus state in wave.do
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2022-06-08 15:30:32 -07:00 |
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slmnemo
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dd33f2a009
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Working version: Fixed error where Word count would always increment even without AHB to bus ACK
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2022-06-08 15:29:32 -07:00 |
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slmnemo
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be658d3933
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Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
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2022-06-08 15:03:15 -07:00 |
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DTowersM
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5bbdddadf8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-08 17:27:23 +00:00 |
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DTowersM
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e3685c1996
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Added my name to the makefile
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2022-06-08 17:27:16 +00:00 |
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DTowersM
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571eb21f41
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-08 16:28:18 +00:00 |
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DTowersM
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38382e3a11
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added #1 delays to Stalls and Flushes in hazard unit
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2022-06-08 16:28:09 +00:00 |
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slmnemo
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a5aa75e5de
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Merge branch 'main' into cacheburstmode
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2022-06-08 02:21:33 +00:00 |
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slmnemo
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1d22fc707a
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Added lock signal to ensure AHB speaks with the right bus
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2022-06-08 02:19:21 +00:00 |
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David Harris
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b53aef33f5
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Modified RAM for single-cycle latency
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2022-06-08 02:06:00 +00:00 |
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David Harris
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cc06fa1c55
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Cleaned bram interface
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2022-06-08 01:39:44 +00:00 |
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David Harris
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f81719337e
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Added ahbapbbridge and cleaning RAM
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2022-06-08 01:31:34 +00:00 |
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DTowersM
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1d41e98504
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-07 23:58:58 +00:00 |
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DTowersM
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3d654fd481
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modified testbench.sv- now works with coremark
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2022-06-07 23:58:50 +00:00 |
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DTowersM
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930c806753
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cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000
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2022-06-07 23:27:54 +00:00 |
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slmnemo
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85801e75db
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Fixed off-by-one error in busdp capture
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2022-06-07 19:36:39 +00:00 |
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Madeleine Masser-Frye
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fcf1cb794e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-07 18:31:54 +00:00 |
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Madeleine Masser-Frye
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8849b47b52
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fixed importing of area-optimized synths, overlayed them on PPA plots, accounted for mux outliers, fixed flop adjustments
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2022-06-07 18:31:49 +00:00 |
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slmnemo
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90c5e5d319
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Reworked bus to handle burst interfacing
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2022-06-07 11:22:53 +00:00 |
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DTowersM
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4cadf139a6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-07 06:03:19 +00:00 |
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DTowersM
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fbfae61ba8
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added support for 64 bit rv tests
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2022-06-07 06:02:23 +00:00 |
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DTowersM
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0e7630dc03
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simplified makefile. Now can call modelsim to run embench runs. Additionally added spike builds to be able to run the embench tests on spike. typing make now builds all necessary files and starts the simulator on the embench
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2022-06-06 22:39:22 +00:00 |
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Katherine Parry
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b8cff98e48
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-06 16:06:54 +00:00 |
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Katherine Parry
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eb93bd46d7
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fma synth warnings and errors removed
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2022-06-06 16:06:04 +00:00 |
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Ross Thompson
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83bca570ae
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Modified debugger for updated rtl.
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2022-06-04 14:39:55 -05:00 |
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slmnemo
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3a276f4c39
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-03 18:56:29 -07:00 |
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slmnemo
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8c3d7b404b
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Fixed recurrent issue with testbench where it would never stop
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2022-06-03 18:56:24 -07:00 |
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cturek
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0e308cfccc
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Added integer division in srt, parametrized everything to work with integers and floating points, parametrized testbench.
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2022-06-04 00:14:10 +00:00 |
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Madeleine Masser-Frye
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fc1860615f
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added area, leakage, energy, adjustment by adder width (N/32)
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2022-06-03 23:51:34 +00:00 |
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Madeleine Masser-Frye
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92d9687ded
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added combined process regression line
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2022-06-03 22:53:03 +00:00 |
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