David Harris
|
7fcc852687
|
Q depends on D
|
2022-08-23 08:29:59 -07:00 |
|
David Harris
|
e714b75888
|
LSU minor edits
|
2022-08-23 07:35:47 -07:00 |
|
David Harris
|
16a92eaf10
|
Updated testbench assertions.
|
2022-08-23 07:23:24 -07:00 |
|
David Harris
|
75a265159b
|
Increased timeout threshold to avoid timeout building riscof tests on slow machine
|
2022-07-27 04:05:21 +00:00 |
|
David Harris
|
9ecef0c4cd
|
fixed testbench merge comflict
|
2022-07-26 06:21:46 -07:00 |
|
David Harris
|
2d7f4b133c
|
More work toward riscof tests
|
2022-07-26 06:19:13 -07:00 |
|
David Harris
|
5c54c5b521
|
Added rv32f tests to RV64gc
|
2022-07-25 23:29:05 +00:00 |
|
Ross Thompson
|
8193946996
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-23 08:41:59 -05:00 |
|
Daniel Torres
|
95fdd408ee
|
commiting current changes to riscof wally tests
|
2022-07-22 11:14:04 -07:00 |
|
Katherine Parry
|
7268b4b334
|
removed underflow from inexactct calculation
|
2022-07-18 17:51:18 +00:00 |
|
Ross Thompson
|
0ef6137ab9
|
Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
|
2022-07-17 21:05:31 -05:00 |
|
Ross Thompson
|
8356e5d742
|
Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
|
2022-07-17 16:20:04 -05:00 |
|
Katherine Parry
|
18d7fee541
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-12 22:37:20 +00:00 |
|
DTowersM
|
fe7d03a3da
|
added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
|
2022-07-11 21:13:09 +00:00 |
|
Katherine Parry
|
97e7e619d9
|
moved fpu ieu write data mux to lsu
|
2022-07-08 23:56:57 +00:00 |
|
David Harris
|
8be1dafbd6
|
Removed testbench code that ignores mismatch on zero signatures
|
2022-07-08 09:17:31 +00:00 |
|
David Harris
|
f865994ba1
|
fixing port errors
|
2022-07-07 21:57:10 +00:00 |
|
David Harris
|
f5bdbbe219
|
Removed sig4 spurious message from testbench
|
2022-07-05 03:27:14 +00:00 |
|
Daniel Torres
|
2ae22ac6cb
|
added changes to testbench, tests and riscof for additional riscof compatability
|
2022-06-29 12:23:40 -07:00 |
|
slmnemo
|
80a57d0469
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-21 02:16:26 -07:00 |
|
slmnemo
|
b2cea45de0
|
Added rudimentary GPIO test according to testplans in chapter 15
|
2022-06-21 02:16:21 -07:00 |
|
Katherine Parry
|
03d823f5d7
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
|
Daniel Torres
|
397783812d
|
embench and testbench now support running both O2 and Os build variations without overwriting one another
|
2022-06-17 21:15:42 -07:00 |
|
Daniel Torres
|
1d4c543f71
|
arch tests now run on spike and sail and compare signatures during build
|
2022-06-17 20:53:15 -07:00 |
|
Daniel Torres
|
0ede7c412e
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
|
475220a5ff
|
arch bug fixes and testbench changes
|
2022-06-17 15:07:16 -07:00 |
|
Katherine Parry
|
5f7072bd96
|
postprocessing unit created and passing all tests
|
2022-06-13 22:47:51 +00:00 |
|
slmnemo
|
a5aa75e5de
|
Merge branch 'main' into cacheburstmode
|
2022-06-08 02:21:33 +00:00 |
|
DTowersM
|
1d41e98504
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-07 23:58:58 +00:00 |
|
DTowersM
|
3d654fd481
|
modified testbench.sv- now works with coremark
|
2022-06-07 23:58:50 +00:00 |
|
DTowersM
|
930c806753
|
cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000
|
2022-06-07 23:27:54 +00:00 |
|
DTowersM
|
4cadf139a6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-07 06:03:19 +00:00 |
|
DTowersM
|
fbfae61ba8
|
added support for 64 bit rv tests
|
2022-06-07 06:02:23 +00:00 |
|
DTowersM
|
23d524b439
|
testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh
|
2022-06-03 22:07:14 +00:00 |
|
David Harris
|
9cd6b309b4
|
Cleaned up test cases in testbench
|
2022-06-02 08:44:28 -07:00 |
|
DTowersM
|
d3c8ee7154
|
added support for embench post processing to testbench.sv
|
2022-06-01 21:00:44 +00:00 |
|
DTowersM
|
2088c0cd7c
|
added testbench.sv support for embench tests, test output still WIP
|
2022-05-31 20:13:32 +00:00 |
|
DTowersM
|
a983791d64
|
fixed indent spacing (cosmetic change)
|
2022-05-26 19:04:21 +00:00 |
|
slmnemo
|
87cfd62e19
|
Added line to testbench to prevent annoying burst sizes
|
2022-05-25 17:29:45 -07:00 |
|
slmnemo
|
5a9e3a852a
|
see commit 9042cc3c
|
2022-05-25 17:10:59 -07:00 |
|
slmnemo
|
d43d340e31
|
added logic to prevent cache line length from exceeding the max size of a burst.
|
2022-05-25 17:03:15 -07:00 |
|
slmnemo
|
a5d5bd272b
|
changes suggested by ben, hopefully fixing buildroot (which is now not running)
|
2022-05-20 18:42:38 -07:00 |
|
slmnemo
|
ba572b46f4
|
Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature.
|
2022-05-17 01:04:13 +00:00 |
|
slmnemo
|
ede0a3237d
|
quit
|
2022-05-17 01:03:09 +00:00 |
|
David Harris
|
730bcac6ba
|
Partitioned privileged pipeline registers into module
|
2022-05-12 20:45:45 +00:00 |
|
David Harris
|
de5b61291f
|
Experiments with prefix comparator; minor fixes in WFI and testbench warnings
|
2022-04-17 21:43:12 +00:00 |
|
Ross Thompson
|
1993069986
|
Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
|
2022-03-30 11:04:15 -05:00 |
|
Ross Thompson
|
fc2b4453ec
|
rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
|
2022-03-29 23:48:19 -05:00 |
|
Ross Thompson
|
de2672231d
|
Partial fix to allow byte write enables with fpga and still get a preload to work.
|
2022-03-29 19:12:29 -05:00 |
|
Ross Thompson
|
d68446cf92
|
Added new asserts to testbench.
|
2022-03-11 15:41:53 -06:00 |
|
bbracker
|
443dd40ea8
|
remove imperas32p tests
|
2022-03-04 00:06:18 +00:00 |
|
bbracker
|
d7b8c9d877
|
add rv32a tests to regression
|
2022-03-02 17:54:55 +00:00 |
|
bbracker
|
4f22a55dd4
|
add LRSC test and add wally64a to regression
|
2022-03-02 07:09:37 +00:00 |
|
bbracker
|
d620fb4442
|
deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
|
2022-03-01 00:37:46 +00:00 |
|
bbracker
|
6caa97bb26
|
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
|
2022-02-22 03:46:08 +00:00 |
|
David Harris
|
e5097e67d4
|
Fixed TIM tests; rv32e test still failing
|
2022-02-08 15:24:37 +00:00 |
|
David Harris
|
e9a519a228
|
Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail
|
2022-02-08 12:40:02 +00:00 |
|
David Harris
|
096242a6d8
|
Merged TIM and regular testbenches. RV32e now working and back in regression.
|
2022-02-08 12:18:13 +00:00 |
|
David Harris
|
23868a33bc
|
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
|
2022-02-05 04:16:18 +00:00 |
|
David Harris
|
16b5fee795
|
RV32e tests
|
2022-02-04 14:30:36 +00:00 |
|
David Harris
|
e92461159d
|
cache cleanup
|
2022-02-03 15:36:11 +00:00 |
|
David Harris
|
9e0055cbb9
|
More config file cleanup; 32ic tests broken
|
2022-02-03 01:08:34 +00:00 |
|
David Harris
|
bdf1a8ba73
|
changed DMEM and IMEM configurations to support BUS/TIM/CACHE
|
2022-02-03 00:41:09 +00:00 |
|
Ross Thompson
|
2f7cf2bc7f
|
Fixed testbench so coremark stops.
|
2022-02-02 11:37:48 -06:00 |
|
Ross Thompson
|
ae36931bb2
|
Added correct stop condition for coremark.
|
2022-02-02 09:53:51 -06:00 |
|
Ross Thompson
|
138b17a399
|
Setup the main regression test to be able to handle coremark.
|
2022-02-01 17:00:11 -06:00 |
|
David Harris
|
62e5c7fd13
|
Comments in LSU code about restructuring
|
2022-01-27 15:53:59 +00:00 |
|
David Harris
|
ca1f7ce5d3
|
Renamed wallypipelinedhart to wallypipelinedcore
|
2022-01-20 16:02:08 +00:00 |
|
David Harris
|
5842d780a7
|
Defined rv32e and rv32emc configs
|
2022-01-17 14:01:01 +00:00 |
|
David Harris
|
f7f3882cb8
|
Moved Dcache into bus block
|
2022-01-15 00:39:07 +00:00 |
|
David Harris
|
37bf5347cf
|
LSU cleanup
|
2022-01-14 23:55:27 +00:00 |
|
Ross Thompson
|
9f7e3f147b
|
Partial local dtim in lsu configuration.
|
2022-01-13 17:50:31 -06:00 |
|
David Harris
|
453a794f86
|
Testbench directory cleanup
|
2022-01-07 17:02:16 +00:00 |
|
David Harris
|
3d2671a8b0
|
Reformatted MIT license to 95 characters
|
2022-01-07 12:58:40 +00:00 |
|
David Harris
|
d17a305538
|
Finished removing generate statements
|
2022-01-05 16:41:17 +00:00 |
|
Ross Thompson
|
888a60d8d6
|
Switched block for line in caches.
|
2022-01-04 22:08:18 -06:00 |
|
David Harris
|
9ddc6db0a6
|
Removed imperas mmu tests; using wallypriv instead
|
2022-01-04 23:14:53 +00:00 |
|
David Harris
|
115287adc8
|
Renamed wally-pipelined to pipelined
|
2022-01-04 19:47:41 +00:00 |
|