Jordan Carlin
c64c6c4cf1
Fix reverted submodules
2024-11-02 16:09:14 -07:00
Rose Thompson
d4fc3245b0
Removed ahbsdc submodule since it is no longer used. Updated old
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submodules pointing to ross144 to rosethompson repos.
2024-10-15 10:11:12 -05:00
Jordan Carlin
4c78cfd0aa
Only ignore untracked changes to testfloat
2024-09-15 15:39:24 -07:00
Jordan Carlin
5d215f3cfe
Ignore testfloat build files
2024-09-15 10:27:09 -07:00
Jordan Carlin
76a4ac4b22
Switch to using testfloat submodule
2024-09-15 00:37:04 -07:00
Jordan Carlin
4fe33415d6
Add softfloat as submodule
2024-09-15 00:20:39 -07:00
Rose Thompson
dc9a77e45a
Updated riscvISACOV submodule to https instead of ssh.
2024-08-29 14:54:47 -07:00
Rose Thompson
a1c6bc854e
Fixed a subtle questa sim bug with imperasDV. On some linux systems
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vsim will default to 32-bit mode rather than 64-bit, but the ImperasDV
libraries are 64-bit. vsim must run in 64-bit mode.
2024-08-29 14:00:52 -07:00
David Harris
bc70f0b933
Merge pull request #869 from jordancarlin/installation
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Installation and setup overhaul
2024-08-08 15:39:23 -07:00
David Harris
77b45f2d75
Fix creating cvw-arch-verif work directory
2024-08-08 05:25:28 -07:00
Jordan Carlin
76eef03fe4
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-08-07 20:22:55 -07:00
Huda-10xe
0303314f4e
Adding RVVI Functional Coverage Support
2024-08-07 14:31:16 +05:00
Jordan Carlin
42a9bbf28d
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-25 21:21:57 -07:00
Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
79d0cb96c2
Added verilog-ethernet as a submodule. Hoping we can make use of sparse-checkout as there are so many files in this repo.
2024-07-18 18:22:26 -05:00
Jordan Carlin
547a859ed8
Clean up .gitmodules file to eliminate warnings when cloning
2024-06-30 11:34:57 -07:00
Jordan Carlin
569ccfd829
Update riscv-arch-test submodule
2024-06-18 23:34:02 -07:00
Rose Thompson
e38b43ae73
Replaced the git@github with hptts:github submodule for ahbsdc which I hope will fix Lee's clone issue
2023-12-11 14:12:38 -06:00
David Harris
d8186b9f58
Swap in branch predictor simulator handling compressed instruction offsets
2023-11-21 16:42:41 -08:00
David Harris
93a0db1fca
swapped branch predictor simulator
2023-11-21 15:02:09 -08:00
Jacob Pease
38cf7f0fb7
ahbsdc submodule actually added this time.
2023-11-16 17:46:48 -06:00
Jacob Pease
ff73f798ed
Replaced vivado-risc-v addins directory with new SDC repo.
2023-11-16 13:59:12 -06:00
David Harris
90cf128349
Added back riscv-arch-test fresh
2023-11-15 05:48:33 -08:00
David Harris
18c29dd7d0
Removed riscv-arch-test submodule that appears corrupted
2023-11-15 05:46:38 -08:00
David Harris
8ba0336c6f
Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e
2023-11-14 11:01:58 -08:00
Ross Thompson
b1f7a5768f
Removed all old references to the old flash card controller.
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Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
026570d3da
Added new submodule for digilent fpga boards.
2023-07-17 16:25:37 -05:00
Victor Clements
9461b9db7e
pulling in FreeRTOS/kernel Submodule
2023-06-13 10:41:18 -07:00
Ross Thompson
f067935eed
Added Yujun Lin's branch predictor simulator. This is a C baseline module for common branch predictor algorithms.
2023-03-07 10:49:59 -06:00
Daniel Torres
16e4260dda
fixed gitmodules
2022-07-21 10:15:13 -07:00
Daniel Torres
e46e96e080
changed the default branch of embench
2022-07-21 10:14:05 -07:00
David Harris
e22d6a2f9a
Removed Sky130 libraries
2022-07-06 13:50:11 +00:00
DTowersM
12f465ea05
added back the .git ignore and .git modules for the coremark directory, also added graphGen to the main repo
2022-06-13 23:33:10 +00:00
DTowersM
39ed36d0ba
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
2022-06-13 23:23:57 +00:00
James Stine
b9480a4643
Added the 12T submodule to the project.
2022-02-03 19:26:41 -06:00
David Harris
069f270d1a
Removed soc_flow
2022-01-31 22:58:33 +00:00
David Harris
c367d19fc6
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-31 00:59:49 +00:00
David Harris
ea85e185f1
gitmodules
2022-01-31 00:59:44 +00:00
James Stine
ef811c7786
Remove book_flow to add back later - will add synthDC back within 30m
2022-01-28 08:18:30 -06:00
David Harris
384cd0d092
Added synthesis submodules
2022-01-27 14:31:34 +00:00
David Harris
de7b9c127e
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
e25760d8e5
Added C test cases
2022-01-11 21:01:48 +00:00
David Harris
07f34c8263
.gitmodule added dirty riscv-arch-test
2021-12-29 23:50:17 +00:00
David Harris
e97e512da9
Started FIR test code and started incorporating Imperas tests
2021-12-25 22:39:51 +00:00
David Harris
434f49c03e
Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead
2021-12-21 02:35:41 +00:00
Kevin Kim
869cd44533
added arch-test submodule
2021-11-30 18:22:08 -08:00
Kevin Kim
6323609da9
Added git submodules
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-riscv-arch-test
-rscv-isa-sim
submodules are added in addins/ directory
2021-11-30 18:16:37 -08:00
kipmacsaigoren
b2677d2090
Added git things to make it all a little nicer and synthesis work.
2021-09-15 12:15:53 -05:00
Teo Ene
1d5d7a7840
Flow updated for 90nm
2021-07-01 13:32:42 -05:00
Teo Ene
bd99a5613a
sky130 18T and 15T cell libraries removed
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Upon noticing their size, concerns were raised about available drive space.
As 12T is the main implementation focus, the decision was made to remove 15T and 18T.
Apologies if any were interested in implementing the processor across multiple standard cell libraries for comparison.
2021-02-14 09:05:41 -06:00
