mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 04:54:29 +00:00
a1c6bc854e
vsim will default to 32-bit mode rather than 64-bit, but the ImperasDV libraries are 64-bit. vsim must run in 64-bit mode.
37 lines
1.3 KiB
Plaintext
37 lines
1.3 KiB
Plaintext
[submodule "addins/riscv-dv"]
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path = addins/riscv-dv
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url = https://github.com/google/riscv-dv
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[submodule "addins/embench-iot"]
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path = addins/embench-iot
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url = https://github.com/embench/embench-iot
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branch = embench-1.0-branch
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[submodule "addins/coremark"]
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path = addins/coremark
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url = https://github.com/eembc/coremark
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[submodule "addins/FreeRTOS-Kernel"]
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path = addins/FreeRTOS-Kernel
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url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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[submodule "addins/vivado-boards"]
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path = addins/vivado-boards
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url = https://github.com/Digilent/vivado-boards/
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[submodule "addins/riscv-arch-test"]
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path = addins/riscv-arch-test
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url = https://github.com/riscv-non-isa/riscv-arch-test
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branch = dev
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[submodule "addins/branch-predictor-simulator"]
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path = addins/branch-predictor-simulator
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url = https://github.com/ross144/branch-predictor-simulator
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[submodule "addins/ahbsdc"]
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path = addins/ahbsdc
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url = https://github.com/JacobPease/ahbsdc.git
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[submodule "addins/verilog-ethernet"]
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sparseCheckout = true
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path = addins/verilog-ethernet
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url = https://github.com/ross144/verilog-ethernet.git
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[submodule "cvw-arch-verif"]
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path = addins/cvw-arch-verif
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url = https://github.com/openhwgroup/cvw-arch-verif
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[submodule "addins/riscvISACOV"]
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path = addins/riscvISACOV
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url = git@github.com:riscv-verification/riscvISACOV.git
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