1038 Commits

Author	SHA1	Message	Date
David Harris	426a43f77b	Forgot to save cacheway merge	2021-10-26 08:38:13 -07:00
David Harris	c0145c0a35	merging changes	2021-10-26 08:34:36 -07:00
David Harris	8287a1ef3e	Synchronous reset in non-flop blocks	2021-10-26 08:30:35 -07:00
Ross Thompson	c43b19120f	Fixed another critical path in the caches.	2021-10-25 22:05:11 -05:00
Ross Thompson	1228dbbebc	Fixed the timing issue in the cache replacement polcy.	2021-10-25 18:00:23 -05:00
Ross Thompson	576383c74b	Fixed bug with the changes to sram1rw.	2021-10-25 16:11:41 -05:00
Ross Thompson	f0beb4357a	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-10-25 15:36:21 -05:00
Ross Thompson	5fd3f7f2c7	Possible fix for critical path timing in caches.	2021-10-25 15:33:33 -05:00
bbracker	39efadf2cf	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-25 12:25:37 -07:00
David Harris	fbee4963da	Converted flops to synchronous reset now that reset signal is synchronized	2021-10-25 11:49:20 -07:00
David Harris	2bf51362e2	Added synchronizer to reset	2021-10-25 10:05:41 -07:00
Ross Thompson	76bba541a7	Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.	2021-10-24 21:21:49 -05:00
bbracker	046a78a8fc	manually resolved git merge conflicts in testbench linux after checkpointing	2021-10-24 15:02:19 -07:00
Ross Thompson	8a51fe76c1	Partial cleanup of unused signals in caches and bpred.	2021-10-24 15:04:20 -05:00
bbracker	36b39358c6	add checkpointing to linux testbench	2021-10-24 06:47:35 -07:00
David Harris	c9e9cd4a60	more lsu/ifu lint cleanup	2021-10-23 12:10:13 -07:00
David Harris	2cfbd888fd	more lsu/ifu lint cleanup	2021-10-23 12:00:32 -07:00
David Harris	62a23fe878	lsu/ifu lint cleanup	2021-10-23 11:41:20 -07:00
David Harris	61fdb3d902	random lint cleanup	2021-10-23 11:24:36 -07:00
David Harris	8d9efcbafb	IEU cleanup	2021-10-23 11:13:28 -07:00
David Harris	4bf823e063	lint cleanup	2021-10-23 11:03:28 -07:00
David Harris	d570df864f	IEU lint cleanup	2021-10-23 10:51:53 -07:00
David Harris	8e516e6391	Lint cleanup from wallypipeliendhart	2021-10-23 10:29:52 -07:00
David Harris	33358d101e	Lint cleanup: ahblite, ifu, hart	2021-10-23 10:12:33 -07:00
David Harris	d24bece3a8	Lint cleanup	2021-10-23 09:58:52 -07:00
David Harris	2e796e3da2	lint cleanup: FPU and privileged	2021-10-23 09:41:24 -07:00
David Harris	c316bff15a	subword read and csrc lint cleanup	2021-10-23 09:29:15 -07:00
David Harris	28d8f6d5cf	FMA and CSRC lint cleanup	2021-10-23 09:20:24 -07:00
David Harris	11b0607e63	Lint cleanup	2021-10-23 09:06:21 -07:00
David Harris	ac1b1bfbb6	update scripts for handling src/*/* subdirectories	2021-10-23 08:54:29 -07:00
David Harris	0dabb6ebd4	lint cleaning and moved files into subdirectories	2021-10-23 08:53:32 -07:00
David Harris	f483e8002a	Lint cleanup	2021-10-23 08:39:21 -07:00
David Harris	e2e950ac0f	Cleaned up LINT erors	2021-10-23 06:28:49 -07:00
David Harris	4c480a40f6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-23 06:15:49 -07:00
David Harris	3249d65209	Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.	2021-10-23 06:15:26 -07:00
James E. Stine	f6e8e45901	Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking	2021-10-22 13:41:50 -05:00
Katherine Parry	7c7c0f538a	put the FMA priority encoders into their own module	2021-10-22 10:03:12 -07:00
James E. Stine	0dcca43f48	Get rid of lint warning - still need more testing though	2021-10-21 15:19:22 -05:00
James E. Stine	dd7dbaa382	Clean up some FPU and add pipelined fpdivsqrt to fpu.sv	2021-10-21 13:52:12 -05:00
James E. Stine	bafb3a983d	Fix fpdivsqrt lint error on CPA for convergence	2021-10-20 17:46:13 -05:00
David Harris	ceaf84a3ce	removed .* from wallypipeliendsoc	2021-10-20 13:49:18 -07:00
James E. Stine	71b48048da	Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.	2021-10-20 12:00:41 -05:00
James E. Stine	41010aa418	Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this	2021-10-19 12:09:43 -05:00
James E. Stine	a75abb04bd	Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2).	2021-10-19 11:58:06 -05:00
David Harris	3bc985d230	Changed some flops to settable	2021-10-18 17:05:29 -07:00
David Harris	0516ee768b	replaced flopenl with flopenr when clearing to 0	2021-10-18 16:53:18 -07:00
David Harris	398337951d	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-18 15:44:31 -07:00
David Harris	00d8035836	Fixed multiplier and pointed arch tests to new path in addins	2021-10-18 15:43:59 -07:00
Ross Thompson	cd58a388e4	fixed issues with dc shell not liking modules with parameters without default values.	2021-10-18 17:24:15 -05:00
James E. Stine	37fe5e56a8	Sanitization some more on mult_cs.sv	2021-10-18 05:24:16 -05:00