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https://github.com/openhwgroup/cvw
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FMA and CSRC lint cleanup
This commit is contained in:
David Harris
parent
11b0607e63
commit
28d8f6d5cf
@ -519,7 +519,7 @@ module fma2(
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///////////////////////////////////////////////////////////////////////////////
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fmaflags fmaflags(.XSNaNM, .YSNaNM, .ZSNaNM, .XInfM, .YInfM, .ZInfM, .XZeroM, .YZeroM,
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.XNaNM, .YNaNM, .ZNaNM, .FullResultExp, .SumExp, .ZSgnEffM, .PSgnM, .Round, .Guard, .UfRound, .UfLSBNormSum, .Sticky, .UfPlus1,
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.XNaNM, .YNaNM, .ZNaNM, .FullResultExp, .SumExp, .ZSgnEffM, .PSgnM, .Round, .Guard, .UfLSBNormSum, .Sticky, .UfPlus1,
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.FmtM, .Invalid, .Overflow, .Underflow, .FMAFlgM);
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@ -799,7 +799,7 @@ module fmaflags(
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input logic [`NE+1:0] FullResultExp, // ResultExp with bits to determine sign and overflow
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input logic [`NE+1:0] SumExp, // exponent of the normalized sum
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input logic ZSgnEffM, PSgnM, // the product and modified Z signs
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input logic Round, Guard, UfRound, UfLSBNormSum, Sticky, UfPlus1, // bits used to determine rounding
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input logic Round, Guard, UfLSBNormSum, Sticky, UfPlus1, // bits used to determine rounding
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input logic FmtM, // precision 1 = double 0 = single
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output logic Invalid, Overflow, Underflow, // flags used to select the result
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output logic [4:0] FMAFlgM // FMA flags
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@ -92,12 +92,10 @@ module csrc #(parameter
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generate
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if (`ZICOUNTERS_SUPPORTED) begin
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// logic [63:0] TIME_REGW, TIMECMP_REGW;
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logic [63:0] CYCLE_REGW, INSTRET_REGW;
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logic [63:0] HPMCOUNTER3_REGW, HPMCOUNTER4_REGW; // add more performance counters here if desired
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logic [63:0] CYCLEPlusM, INSTRETPlusM;
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logic [63:0] HPMCOUNTER3PlusM, HPMCOUNTER4PlusM;
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// logic [`XLEN-1:0] NextTIMEM;
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logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
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logic [`XLEN-1:0] NextHPMCOUNTER3M, NextHPMCOUNTER4M;
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logic WriteCYCLEM, WriteINSTRETM;
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@ -108,27 +106,15 @@ module csrc #(parameter
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assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
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//logic [`COUNTERS-1:3][`XLEN-1:0] HPMCOUNTERH_REGW;
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// Write enables
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// assign WriteTIMEM = CSRMWriteM && (CSRAdrM == MTIME);
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// assign WriteTIMECMPM = CSRMWriteM && (CSRAdrM == MTIMECMP);
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assign WriteCYCLEM = CSRMWriteM && (CSRAdrM == MCYCLE);
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assign WriteINSTRETM = CSRMWriteM && (CSRAdrM == MINSTRET);
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//assign WriteHPMCOUNTER3M = CSRMWriteM && (CSRAdrM == MHPMCOUNTER3);
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//assign WriteHPMCOUNTER4M = CSRMWriteM && (CSRAdrM == MHPMCOUNTER4);
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// Counter adders with inhibits for power savings
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assign CYCLEPlusM = CYCLE_REGW + {63'b0, ~MCOUNTINHIBIT_REGW[0]};
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//assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited
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assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidNotFlushedM & ~MCOUNTINHIBIT_REGW[2]};
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//assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls
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//assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals
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assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0];
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//assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[`XLEN-1:0];
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assign NextINSTRETM = WriteINSTRETM ? CSRWriteValM : INSTRETPlusM[`XLEN-1:0];
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//assign NextHPMCOUNTER3M = WriteHPMCOUNTER3M ? CSRWriteValM : HPMCOUNTER3PlusM[`XLEN-1:0];
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//assign NextHPMCOUNTER4M = WriteHPMCOUNTER4M ? CSRWriteValM : HPMCOUNTER4PlusM[`XLEN-1:0];
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// parameterized number of additional counters
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if (`COUNTERS > 3) begin
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@ -170,7 +156,6 @@ module csrc #(parameter
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always @(posedge clk, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
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if (reset) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 0;
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else if (~StallW) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
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//flopr #(`XLEN) HPMCOUNTERreg[i](clk, reset, NextHPMCOUNTERM[i], HPMCOUNTER_REGW[i]);
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if (`XLEN==32) begin
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logic [`COUNTERS-1:3] WriteHPMCOUNTERHM;
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@ -181,7 +166,6 @@ module csrc #(parameter
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always @(posedge clk, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
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if (reset) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 0;
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else if (~StallW) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
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//flopr #(`XLEN) HPMCOUNTERHreg[i](clk, reset, NextHPMCOUNTERHM[i], HPMCOUNTER_REGW[i][63:32]);
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end else begin
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assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
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end
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@ -191,44 +175,23 @@ module csrc #(parameter
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// Write / update counters
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// Only the Machine mode versions of the counter CSRs are writable
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if (`XLEN==64) begin// 64-bit counters
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// flopr #(64) TIMEreg(clk, reset, WriteTIMEM ? CSRWriteValM : TIME_REGW + 1, TIME_REGW); // may count off a different clock***
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// flopenr #(64) TIMECMPreg(clk, reset, WriteTIMECMPM, CSRWriteValM, TIMECMP_REGW);
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flopr #(64) CYCLEreg(clk, reset, NextCYCLEM, CYCLE_REGW);
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flopr #(64) INSTRETreg(clk, reset, NextINSTRETM, INSTRET_REGW);
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//flopr #(64) HPMCOUNTER3reg(clk, reset, NextHPMCOUNTER3M, HPMCOUNTER3_REGW);
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//flopr #(64) HPMCOUNTER4reg(clk, reset, NextHPMCOUNTER4M, HPMCOUNTER4_REGW);
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end else begin // 32-bit low and high counters
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end else begin // 32-bit low and high counters
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logic WriteTIMEHM, WriteTIMECMPHM, WriteCYCLEHM, WriteINSTRETHM;
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//logic WriteHPMCOUNTER3HM, WriteHPMCOUNTER4HM;
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logic [`XLEN-1:0] NextCYCLEHM, NextTIMEHM, NextINSTRETHM;
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//logic [`XLEN-1:0] NextHPMCOUNTER3HM, NextHPMCOUNTER4HM;
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// Write Enables
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// assign WriteTIMEHM = CSRMWriteM && (CSRAdrM == MTIMEH);
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// assign WriteTIMECMPHM = CSRMWriteM && (CSRAdrM == MTIMECMPH);
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assign WriteCYCLEHM = CSRMWriteM && (CSRAdrM == MCYCLEH);
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assign WriteINSTRETHM = CSRMWriteM && (CSRAdrM == MINSTRETH);
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//assign WriteHPMCOUNTER3HM = CSRMWriteM && (CSRAdrM == MHPMCOUNTER3H);
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//assign WriteHPMCOUNTER4HM = CSRMWriteM && (CSRAdrM == MHPMCOUNTER4H);
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assign NextCYCLEHM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[63:32];
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// assign NextTIMEHM = WriteTIMEHM ? CSRWriteValM : TIMEPlusM[63:32];
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assign NextINSTRETHM = WriteINSTRETHM ? CSRWriteValM : INSTRETPlusM[63:32];
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//assign NextHPMCOUNTER3HM = WriteHPMCOUNTER3HM ? CSRWriteValM : HPMCOUNTER3PlusM[63:32];
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//assign NextHPMCOUNTER4HM = WriteHPMCOUNTER4HM ? CSRWriteValM : HPMCOUNTER4PlusM[63:32];
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// Counter CSRs
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// flopr #(32) TIMEreg(clk, reset, NextTIMEM, TIME_REGW); // may count off a different clock***
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// flopenr #(32) TIMECMPreg(clk, reset, WriteTIMECMPM, CSRWriteValM, TIMECMP_REGW[31:0]);
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flopr #(32) CYCLEreg(clk, reset, NextCYCLEM, CYCLE_REGW[31:0]);
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flopr #(32) INSTRETreg(clk, reset, NextINSTRETM, INSTRET_REGW[31:0]);
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//flopr #(32) HPMCOUNTER3reg(clk, reset, NextHPMCOUNTER3M, HPMCOUNTER3_REGW[31:0]);
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//flopr #(32) HPMCOUNTER4reg(clk, reset, NextHPMCOUNTER4M, HPMCOUNTER4_REGW[31:0]);
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// flopr #(32) TIMEHreg(clk, reset, NextTIMEHM, TIME_REGW); // may count off a different clock***
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// flopenr #(32) TIMECMPHreg(clk, reset, WriteTIMECMPHM, CSRWriteValM, TIMECMP_REGW[63:32]);
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flopr #(32) CYCLEHreg(clk, reset, NextCYCLEHM, CYCLE_REGW[63:32]);
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flopr #(32) INSTRETHreg(clk, reset, NextINSTRETHM, INSTRET_REGW[63:32]);
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//flopr #(32) HPMCOUNTER3Hreg(clk, reset, NextHPMCOUNTER3HM, HPMCOUNTER3_REGW[63:32]);
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//flopr #(32) HPMCOUNTER4Hreg(clk, reset, NextHPMCOUNTER4HM, HPMCOUNTER4_REGW[63:32]);
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end
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// eventually move TIME and TIMECMP to the CLINT -- Ben 06/17/21: sure let's give that a shot!
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@ -253,13 +216,9 @@ module csrc #(parameter
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MTIMECMP: CSRCReadValM = MTIMECMP_CLINT;
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MCYCLE: CSRCReadValM = CYCLE_REGW;
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MINSTRET: CSRCReadValM = INSTRET_REGW;
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//MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW;
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//MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW;
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TIME: CSRCReadValM = MTIME_CLINT;
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CYCLE: CSRCReadValM = CYCLE_REGW;
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INSTRET: CSRCReadValM = INSTRET_REGW;
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//HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW;
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//HPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW;
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default: begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1;
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@ -282,24 +241,16 @@ module csrc #(parameter
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MTIMECMP: CSRCReadValM = MTIMECMP_CLINT[31:0];
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MCYCLE: CSRCReadValM = CYCLE_REGW[31:0];
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MINSTRET: CSRCReadValM = INSTRET_REGW[31:0];
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//MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0];
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//MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0];
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TIME: CSRCReadValM = MTIME_CLINT[31:0];
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CYCLE: CSRCReadValM = CYCLE_REGW[31:0];
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INSTRET: CSRCReadValM = INSTRET_REGW[31:0];
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//HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0];
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//HPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0];
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MTIMEH: CSRCReadValM = MTIME_CLINT[63:32];
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MTIMECMPH: CSRCReadValM = MTIMECMP_CLINT[63:32];
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MCYCLEH: CSRCReadValM = CYCLE_REGW[63:32];
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MINSTRETH: CSRCReadValM = INSTRET_REGW[63:32];
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//MHPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32];
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//MHPMCOUNTER4H: CSRCReadValM = HPMCOUNTER4_REGW[63:32];
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TIMEH: CSRCReadValM = MTIME_CLINT[63:32];
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CYCLEH: CSRCReadValM = CYCLE_REGW[63:32];
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INSTRETH: CSRCReadValM = INSTRET_REGW[63:32];
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//HPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32];
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//HPMCOUNTER4H: CSRCReadValM = HPMCOUNTER4_REGW[63:32];
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default: begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1;
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@ -316,216 +267,3 @@ module csrc #(parameter
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endgenerate
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endmodule
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/* Bad code from class
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///////////////////////////////////////////
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// csrc.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:ssanghai@hmc.edu 2nd March
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// Added a configurable number of counters
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// dottolia@hmc.edu 20 April 2021
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// Make counters synthesizable
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//
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// Purpose: Counter CSRs
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// See RISC-V Privileged Mode Specification 20190608 3.1.10-11
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module csrc #(parameter
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// counters
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MHPMCOUNTERBASE = 12'hB00,
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MHPMCOUNTERHBASE = 12'hB80,
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MPHMEVENTBASE = 12'h320,
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HPMCOUNTERBASE = 12'hC00,
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HPMCOUNTERHBASE = 12'hC80,
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)(input logic clk, reset,
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input logic StallD, StallE, StallM, StallW,
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input logic InstrValidM, LoadStallD, CSRMWriteM,
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input logic BPPredDirWrongM,
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input logic BTBPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic BPPredClassNonCFIWrongM,
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input logic [4:0] InstrClassM,
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input logic [11:0] CSRAdrM,
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
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output logic [`XLEN-1:0] CSRCReadValM,
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output logic IllegalCSRCAccessM);
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// counters
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// create Counter arrays to store address of each counter
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integer MHPMCOUNTER [`COUNTERS:0];
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integer MHPMCOUNTERH [`COUNTERS:0];
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integer HPMCOUNTER [`COUNTERS:0];
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integer HPMCOUNTERH [`COUNTERS:0];
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integer MHPEVENT [`COUNTERS:0];
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genvar i;
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// *** this is totally incorrect. Fix parameterized counters dh 6/9/21
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generate
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for (i = 0; i <= `COUNTERS; i = i + 1) begin
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if (i != 1) begin
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always @(posedge reset) begin
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MHPMCOUNTER[i] = 12'hB00 + i; // not sure this addition is legit
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MHPMCOUNTERH[i] = 12'hB80 + i;
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HPMCOUNTER[i] = 12'hC00 + i;
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HPMCOUNTERH[i] = 12'hC80 + i;
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MHPEVENT[i] = 12'h320 + i; // MHPEVENT[0] = MCOUNTERINHIBIT
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end
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end
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end //end for loop
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endgenerate
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logic [`COUNTERS:0] MCOUNTEN;
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assign MCOUNTEN[0] = 1'b1;
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assign MCOUNTEN[1] = 1'b0;
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assign MCOUNTEN[2] = InstrValidM & ~StallW;
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assign MCOUNTEN[3] = LoadStallD & ~StallD;
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assign MCOUNTEN[4] = BPPredDirWrongM & ~StallM;
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assign MCOUNTEN[5] = InstrClassM[0] & ~StallM;
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assign MCOUNTEN[6] = BTBPredPCWrongM & ~StallM;
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assign MCOUNTEN[7] = (InstrClassM[4] | InstrClassM[2] | InstrClassM[1]) & ~StallM;
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assign MCOUNTEN[8] = RASPredPCWrongM & ~StallM;
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assign MCOUNTEN[9] = InstrClassM[3] & ~StallM;
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assign MCOUNTEN[10] = BPPredClassNonCFIWrongM & ~StallM;
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assign MCOUNTEN[`COUNTERS:11] = 0;
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genvar j;
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generate
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if (`ZICOUNTERS_SUPPORTED) begin
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logic [`COUNTERS:0][63:0] HPMCOUNTER_REGW;
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logic [`COUNTERS:0][63:0] HPMCOUNTERPlusM;
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logic [`COUNTERS:0][`XLEN-1:0] NextHPMCOUNTERM;
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logic [`COUNTERS:0] WriteHPMCOUNTERM;
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logic [4:0] CounterNumM;
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assign CounterNumM = CSRAdrM[4:0]; // which counter to read? ***
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for (j=0; j<= `COUNTERS; j = j+1) begin
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// Write enables
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if (j != 1) begin
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assign WriteHPMCOUNTERM[j] = CSRMWriteM && (CSRAdrM == MHPMCOUNTER[j]);
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// Count Signals
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assign HPMCOUNTERPlusM[j] = HPMCOUNTER_REGW[j] + {63'b0, MCOUNTEN[j] & ~MCOUNTINHIBIT_REGW[j]};
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assign NextHPMCOUNTERM[j] = WriteHPMCOUNTERM[j] ? CSRWriteValM : HPMCOUNTERPlusM[j][`XLEN-1:0];
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end
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// Write / update counters
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// Only the Machine mode versions of the counter CSRs are writable
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if (`XLEN==64) begin // 64-bit counters
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flopenr #(64) HPMCOUNTERreg_j(clk, reset, ~StallW, NextHPMCOUNTERM[j], HPMCOUNTER_REGW[j]);
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end
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else begin // 32-bit low and high counters
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logic [`COUNTERS:0] WriteHPMCOUNTERHM;
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logic [`COUNTERS:0] [`XLEN-1:0] NextHPMCOUNTERHM;
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// Write Enables
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assign WriteHPMCOUNTERHM[j] = CSRMWriteM && (CSRAdrM == MHPMCOUNTERH[j]);
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assign NextHPMCOUNTERHM[j] = WriteHPMCOUNTERHM[j] ? CSRWriteValM : HPMCOUNTERPlusM[j][63:32];
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// Counter CSRs
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flopenr #(32) HPMCOUNTERreg_j(clk, reset, ~StallW, NextHPMCOUNTERM[j], HPMCOUNTER_REGW[j][31:0]);
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flopenr #(32) HPMCOUNTERHreg_j(clk, reset, ~StallW, NextHPMCOUNTERHM[j], HPMCOUNTER_REGW[j][63:32]);
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end
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end // end for
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// eventually move TIME and TIMECMP to the CLINT
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// run TIME off asynchronous reference clock
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// synchronize write enable to TIME
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// four phase handshake to synchronize reads from TIME
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// interrupt on timer compare
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// ability to disable optional CSRs
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// Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
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if (`XLEN==64) begin // 64-bit counter reads
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always_comb
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if (PrivilegeModeW == `M_MODE ||
|
||||
MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
|
||||
|
||||
if (CSRAdrM[11:5] == MHPMCOUNTER[0][11:5] || CSRAdrM[11:5] == HPMCOUNTER[0][11:5]) begin
|
||||
CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM[4:0]];
|
||||
IllegalCSRCAccessM = 0;
|
||||
end
|
||||
// //case (CSRAdrM)
|
||||
// MHPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j];
|
||||
// HPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j];
|
||||
// default: begin
|
||||
// CSRCReadValM = 0;
|
||||
// IllegalCSRCAccessM = 1;
|
||||
// end
|
||||
// endcase
|
||||
// end
|
||||
else begin
|
||||
IllegalCSRCAccessM = 1; // no privileges for this csr
|
||||
CSRCReadValM = 0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
IllegalCSRCAccessM = 1; // no privileges for this csr
|
||||
CSRCReadValM = 0;
|
||||
end
|
||||
end
|
||||
else begin // 32-bit counter reads
|
||||
always_comb
|
||||
if (PrivilegeModeW == `M_MODE ||
|
||||
MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
|
||||
|
||||
if (CSRAdrM[11:5] == MHPMCOUNTER[0][11:5] || CSRAdrM[11:5] == HPMCOUNTER[0][11:5] ||
|
||||
CSRAdrM[11:5] == MHPMCOUNTERH[0][11:5] || CSRAdrM[11:5] == HPMCOUNTERH[0][11:5]) begin
|
||||
CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM[4:0]];
|
||||
IllegalCSRCAccessM = 0;
|
||||
end
|
||||
|
||||
else begin
|
||||
IllegalCSRCAccessM = 1; // no privileges for this csr
|
||||
CSRCReadValM = 0;
|
||||
end
|
||||
|
||||
// IllegalCSRCAccessM = 0;
|
||||
// case (CSRAdrM)
|
||||
// MHPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j][31:0];
|
||||
// HPMCOUNTER[j]: CSRCReadValM = HPMCOUNTER_REGW[j][31:0];
|
||||
// MHPMCOUNTERH[j]: CSRCReadValM = HPMCOUNTER_REGW[j][63:32];
|
||||
// HPMCOUNTERH[j]: CSRCReadValM = HPMCOUNTER_REGW[j][63:32];
|
||||
// default: begin
|
||||
// CSRCReadValM = 0;
|
||||
// IllegalCSRCAccessM = 1;
|
||||
// end
|
||||
// endcase
|
||||
end
|
||||
else begin
|
||||
IllegalCSRCAccessM = 1; // no privileges for this csr
|
||||
CSRCReadValM = 0;
|
||||
end
|
||||
end // 32-bit counter end
|
||||
end // end for big if
|
||||
else begin
|
||||
assign CSRCReadValM = 0;
|
||||
assign IllegalCSRCAccessM = 1;
|
||||
end // end for else
|
||||
endgenerate
|
||||
endmodule
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user