David Harris
4285d60041
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:37:56 -04:00
David Harris
8758b6efa1
Flush uart print statements on \n
2021-05-03 19:37:45 -04:00
Elizabeth Hedenberg
08bfaeffe3
coremark print statment
2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
800f799b7c
coremark updates
2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
d06ad058a4
coremark update
2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
9e0ce2de61
Coremark objump push
2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
81ed9b5d06
coremark directory changes
2021-05-03 19:35:06 -04:00
David Harris
2f5649832a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:29:01 -04:00
David Harris
1f2da4c457
Flush uart print statements on \n
2021-05-03 19:25:28 -04:00
Ross Thompson
6a01ea9f2d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:57:36 -05:00
Domenico Ottolia
e59f8037be
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:56:05 -04:00
Ross Thompson
21c0ee0cf2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:56:00 -05:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Domenico Ottolia
ab68933466
Fix bug that caused stvec to get the wrong value
2021-05-03 17:54:57 -04:00
Thomas Fleming
3f7061d557
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:38:13 -04:00
Thomas Fleming
86a93d77b4
Implement PMP checker and revise PMA checker
2021-05-03 17:37:42 -04:00
Thomas Fleming
00c3b5a033
Remove remnants of InstrReadC
2021-05-03 17:36:25 -04:00
Jarred Allen
a21b84e2ad
Add lint to regression
2021-05-03 17:32:05 -04:00
Ross Thompson
0a44d4dd4e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 14:53:54 -05:00
Ross Thompson
e09ac73eaf
Removed combinational loops between icache and PMA checker.
2021-05-03 14:51:25 -05:00
Ross Thompson
7185905f7b
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
David Harris
699a8f3ac3
Extended maximum signature length to 1M
2021-05-03 15:29:20 -04:00
Katherine Parry
3f05e31954
fpu warnings fixed/commented
2021-05-03 19:17:09 +00:00
Thomas Fleming
94d734cca9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Ross Thompson
12b978fec2
Eliminated extra register and fixed ports to icache.
...
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
bbracker
8ec0d18444
merge conflict resolved -- Ross and I made the same fix
2021-05-03 10:10:42 -04:00
bbracker
1db608fbc6
small rv64 plic test bugfix
2021-05-03 10:06:44 -04:00
Ross Thompson
fdf4954a20
Added back in function name to wave.do
2021-05-03 09:04:48 -05:00
Ross Thompson
b57c187208
Fixed typo in ifu for bypassing branch predictor.
...
Fixed missing signal name in local history predictor.
2021-05-03 08:56:45 -05:00
David Harris
c9806fb472
Fixed lint error in div
2021-05-03 09:26:12 -04:00
bbracker
fb0910d9c0
ifu lint fixes
2021-05-03 09:25:22 -04:00
bbracker
acd99be7f8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 09:23:52 -04:00
Noah Boorstin
491212c499
ok should be the final parsing script change from me
2021-05-03 01:37:24 -04:00
Noah Boorstin
de4dd848c8
buildroot: add one final utility script
2021-05-03 01:28:09 -04:00
Noah Boorstin
8d417558ae
busybear: remove now unneeded hack for fixed CSR issue
2021-05-01 15:17:04 -04:00
Katherine Parry
9252d08b41
fpu imperas tests run
2021-05-01 02:18:01 +00:00
bbracker
0d62440f60
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-30 06:26:35 -04:00
bbracker
9c08ce5359
rv32 plic test and lint fixes
2021-04-30 06:26:31 -04:00
Noah Boorstin
c9fcd3405d
rollback regression to 400k instrs for busybear
2021-04-29 20:59:30 -04:00
Domenico Ottolia
830787e3e1
Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
2021-04-29 20:42:14 -04:00
Ross Thompson
893e03d55b
Fixed memory size in configs for rv32ic and rv64ic.
...
Removed warning on call to $fscanf.
2021-04-29 17:36:46 -05:00
Domenico Ottolia
8eb5195637
Add .S files for new mcause and scause tests
2021-04-29 16:48:56 -04:00
Domenico Ottolia
750d276feb
Minor improvements to scause test
2021-04-29 16:48:07 -04:00
Domenico Ottolia
f18acc1476
Add .S and .reference_output files for mie tests
2021-04-29 16:40:48 -04:00
Domenico Ottolia
fdbd238a87
Add machine-mode timer interrupts to mcause tests
2021-04-29 16:39:18 -04:00
Thomas Fleming
10c7260980
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-29 16:30:00 -04:00
Domenico Ottolia
c9cb2f51d1
Same but don't break sim-wally this time
2021-04-29 15:33:27 -04:00
Domenico Ottolia
fdd4deec2f
Add more exceptions to medeleg tests
2021-04-29 15:32:13 -04:00
ushakya22
de23edcfb9
fix to pcm bug
2021-04-29 15:21:08 -04:00
ushakya22
f139f248dc
Working MIE timer tests
2021-04-29 15:19:43 -04:00
