Github_Repos/cvw
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6,954 Commits 5 Branches 2 Tags 53 MiB
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42 Commits

Author SHA1 Message Date
David Harris
388d699baa Cleaned up lint for plic_apb part select 2023-07-30 02:00:38 -07:00
David Harris
54d6a1afa2 Fixed Questa warnings in plic_apb about part select out of bounds 2023-07-30 01:54:41 -07:00
Ross Thompson
717833b11a Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
Ross Thompson
6099b0e763 Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Jacob Pease
142ec857ed Modified bootloader to access GUID partitions. SDC interrupt to PLIC. 
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.

The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself  was modified to accept the
SDC interrupt signal.
 2023-07-14 13:36:44 -05:00
Ross Thompson
40b2f7ff9c Updated comments. 2023-07-06 15:24:26 -05:00
Ross Thompson
dc50ddd75e Removed unused parameter. 2023-07-06 14:57:07 -05:00
Ross Thompson
18278b7f4d It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga. 2023-07-06 14:07:37 -05:00
Ross Thompson
ba9d5287d9 This is at least functionally correct, but has verilator lint issues. 2023-07-06 11:53:34 -05:00
Ross Thompson
930aed0898 closer, but the wally32/64priv tests are failing. 2023-07-05 17:47:38 -05:00
Ross Thompson
c0fdd3fbca Partially solved fpga boot. 2023-07-05 17:30:55 -05:00
Ross Thompson
2f35bec970 FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. 2023-06-16 15:40:13 -05:00
Ross Thompson
6d31936e89 Added comment to uart LCR to check reset value after updating FPGA. 2023-06-15 15:39:51 -05:00
Ross Thompson
34d1d50b87 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
a011b7d591 Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
2fc8080102 Got the srams parameterized correctly now. 2023-06-15 13:42:24 -05:00
David Harris
e0b6a2d693 Fixed UART merge conflict 2023-06-15 11:36:37 -07:00
Harshini Srinath
e9cfbd95f4
Update uncore.sv 
Program clean up
 2023-06-15 10:23:47 -07:00
Harshini Srinath
5d8e120031
Update uart_apb.sv 
Program clean up
 2023-06-15 10:21:46 -07:00
Harshini Srinath
53ad51ae54
Update uartPC16550D.sv 
Program clean up
 2023-06-15 10:20:29 -07:00
Harshini Srinath
ae165b35f9
Update rom_ahb.sv 
Program clean up
 2023-06-15 10:13:15 -07:00
Harshini Srinath
97917c2a44
Update ram_ahb.sv 
Program clean up
 2023-06-15 10:10:38 -07:00
Harshini Srinath
a9495e8595
Update plic_apb.sv 
Program clean up
 2023-06-15 10:08:16 -07:00
Harshini Srinath
afa0bcdd16
Update gpio_apb.sv 
Program clean up
 2023-06-15 10:04:28 -07:00
Harshini Srinath
83acb77507
Update clint_apb.sv 
Program clean up
 2023-06-15 09:59:11 -07:00
David Harris
380c9e1dde Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-15 07:01:44 -07:00
David Harris
59bf356064 Removed *** from UART code 2023-06-14 08:47:01 -07:00
David Harris
ea805d32ec Removed QEMU from UART 2023-06-14 08:39:01 -07:00
Harshini Srinath
58c617c548
Update ahbapbbridge.sv 
Program clean up
 2023-06-12 20:49:46 -07:00
Ross Thompson
e56497101a Updated source code to be compatible with verilator 5.011 for lint only. 2023-05-31 10:44:23 -05:00
Ross Thompson
ab91fe7436 Cleanup parameterization for verilator 5.010. 2023-05-31 10:02:34 -05:00
Ross Thompson
b8474b208e Uncore is now parameterized. 2023-05-26 16:24:12 -05:00
Jacob Pease
2ad9c72acc The Vivado-RISC-V SDC works. Wally is now booting through it. 2023-05-26 15:42:33 -05:00
Ross Thompson
3765ebfb9f PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue. 2023-05-26 11:06:48 -05:00
Jacob Pease
2b9e5608a4 Build doesn't work. AXI Crossbar has problems. 2023-04-06 16:01:58 -05:00
Ross Thompson
3fc0c4b34e Modified plic and uart to remove async reset. This removes vivado critical warning. 2023-03-24 20:37:48 -05:00
Ross Thompson
78ab9f59af Updated GPIO signal names to reflect book. 2023-03-24 18:55:43 -05:00
Ross Thompson
730f3ac84e Fixed all tap/space issue in RTL. 2023-03-24 17:32:25 -05:00
Jacob Pease
303c997a69 Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore 2023-03-24 17:01:27 -05:00
Jacob Pease
5161fd25cc Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-02-16 17:36:26 -06:00
David Harris
99d179dd3e Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00