Ross Thompson 3dd89a7e62 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2021-07-22 10:38:24 -05:00
..
cache	Tested all numbers of ways for dcache 1, 2, 4, and 8.	2021-07-22 10:38:07 -05:00
ebu	moved subwordread to lsu	2021-07-17 20:37:20 -04:00
fpu	FDIV and FSQRT work	2021-07-21 14:08:14 -04:00
generic	renamed or_rows.sv	2021-07-16 20:17:03 -04:00
hazard	Renamed DCacheStall to LSUStall in hart and hazard.	2021-07-15 10:16:16 -05:00
ieu	Merge branch 'main' into dcache	2021-07-15 11:55:20 -05:00
ifu	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-21 16:44:32 -05:00
lsu	Improved address bus names and usages in the walker, dcache, and tlbs.	2021-07-21 14:55:09 -05:00
mmu	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-21 16:44:32 -05:00
muldiv	Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported	2021-07-04 19:33:46 -04:00
privileged	fixed issue with tlbflush remaining high during a stalled sfence instruction	2021-07-21 17:43:36 -04:00
uncore	fix UART RX FIFO bug where tail pointer can overtake head pointer	2021-07-22 02:09:41 -04:00
wally	Added performance counters for dcache access and dcache miss.	2021-07-19 22:12:20 -05:00