20 Commits

Author	SHA1	Message	Date
slmnemo	cc8acd947d	Fixed lint error	2022-06-09 17:22:04 -07:00
David Harris	c1a40a15dd	New RAM for further testing	2022-06-09 23:50:43 +00:00
David Harris	b53aef33f5	Modified RAM for single-cycle latency	2022-06-08 02:06:00 +00:00
David Harris	cc06fa1c55	Cleaned bram interface	2022-06-08 01:39:44 +00:00
David Harris	f81719337e	Added ahbapbbridge and cleaning RAM	2022-06-08 01:31:34 +00:00
David Harris	462158ea92	LSU name cleanup	2022-04-18 03:18:38 +00:00
Ross Thompson	1586f893b1	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 16:30:55 -05:00
Ross Thompson	e81f317764	Notes on what to change in ram.sv.	2022-03-31 15:48:15 -05:00
Ross Thompson	370a075fa1	Partial cleanup of memories.	2022-03-30 11:09:21 -05:00
Ross Thompson	de2672231d	Partial fix to allow byte write enables with fpga and still get a preload to work.	2022-03-29 19:12:29 -05:00
Ross Thompson	d8947fa616	cleanup of ram.sv	2022-03-11 18:09:22 -06:00
Ross Thompson	54abd944e2	Simplified byte write enable logic.	2022-03-10 18:13:35 -06:00
Ross Thompson	50789f9ddd	Byte write enables are passing all configs now.	2022-03-10 17:26:32 -06:00
Ross Thompson	f7df3a0666	Progress on the path to getting all configs working with byte write enables.	2022-03-10 17:02:52 -06:00
Ross Thompson	99bb281944	Updated fpga's bootloader to reflect the changes to the gpio address change.	2022-02-01 10:43:24 -06:00
David Harris	ca1f7ce5d3	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
Ross Thompson	9f7e3f147b	Partial local dtim in lsu configuration.	2022-01-13 17:50:31 -06:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	6d4714651c	Removed more generate statements	2022-01-05 16:25:08 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00