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2,185 Commits 5 Branches 2 Tags 53 MiB
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53 Commits

Author SHA1 Message Date
David Harris
865d5ce0b1 Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
David Harris
ecce1e62ee changed ideal memory to MEM_DTIM and MEM_ITIM 2021-12-14 13:05:32 -08:00
Ross Thompson
b03ca464f1 Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
Ross Thompson
de4ea16d32 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
Shreya Sanghai
4424006624 added DESIGN_COMPLIER to forgotten config files 2021-10-12 10:14:04 -07:00
Ross Thompson
f6c6cb9ed2 Merge branch 'main' into fpga 2021-10-11 18:17:58 -05:00
David Harris
2ae51d1852 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
Ross Thompson
7ca801113e Added debugging directives to system verilog. 2021-09-27 13:57:46 -05:00
Ross Thompson
80e37d2291 Added SDC defines to each config mode. 
Added sd_top which is the sd card reader.
 2021-09-24 12:24:30 -05:00
David Harris
9ae25b0cea Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
Ross Thompson
c749d08542 fixed the read timer issue but we still have problems with interrupts and i/o devices. 2021-08-06 10:16:06 -05:00
David Harris
e1a1a8395e Parameterized I$/D$ configurations and added sanity check assertions in testbench 2021-07-20 08:57:13 -04:00
David Harris
4d40b5faef Added cache configuration to config files 2021-07-19 18:19:46 -04:00
David Harris
80666f0a71 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00
David Harris
9645b023c9 Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
bbracker
23f479d225 remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR 2021-06-20 22:38:25 -04:00
David Harris
35c74348a4 allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
679e507cc6 Added SUPPORTED to each peripheral in each config file 2021-06-17 21:36:32 -04:00
David Harris
0ffbd03139 More verilator fixes, but bpred is broken 2021-06-09 21:03:03 -04:00
Kip Macsai-Goren
a95a7a7b82 working version with new mmu comments, old boottim values 2021-06-08 15:20:25 -04:00
David Harris
b613f46c2d Resized BOOT TIM to 1 KB 2021-06-08 14:04:32 -04:00
David Harris
2ae5ca19b5 Continued merge 2021-06-07 12:49:47 -04:00
David Harris
ff62000e2c Second attept to commit refactoring config files 2021-06-07 12:37:46 -04:00
David Harris
dc0b19dfaa Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
d5ec797ba4 Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
Kip Macsai-Goren
22e8e06ac7 moved privilege dfinitions into wally-constants, upgraded relevant includes 2021-06-04 17:55:07 -04:00
David Harris
a26bf37be8 Started MMU 2021-06-04 11:59:14 -04:00
David Harris
0674f5506e moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
Kip Macsai-Goren
40cfa86935 Edited and added constants to support SV48 2021-06-01 17:49:45 -04:00
Ross Thompson
72363f5c66 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Ross Thompson
6e803b724e Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
Noah Boorstin
6954e6df4c buildroot: sim is now running! 
yes it only gets through 5 instructions right now. Yes that's my fault.
 2021-04-17 14:44:32 -04:00
Thomas Fleming
303c2c4839 Implement support for superpages 2021-04-08 02:44:59 -04:00
bbracker
31c6b2d01f Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Ross Thompson
e1842c8da6 Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses. 2021-03-23 13:54:59 -05:00
bbracker
11d4a8ab34 first pass at PLIC interface 2021-03-22 10:14:21 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
1091dd10c1 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Noah Boorstin
bc1a0c6ee7 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Noah Boorstin
a2b0af460e everyone gets a bootram 2021-03-18 12:35:37 -04:00
Elizabeth Hedenberg
da758e9e14 Merge branch '3_3_2021' into main 
Making sure coremark works with spring break changes
 2021-03-17 14:11:37 -04:00
Shreya Sanghai
36f0631203 added gshare and global history predictor 2021-03-16 17:03:01 -04:00
Shreya Sanghai
9eed875886 added global history branch predictor 2021-03-16 16:06:40 -04:00
Shreya Sanghai
74f1641c5a Merge branch 'counters' into main 
added a configurable number of performance counters
 2021-03-16 11:01:30 -04:00
Ross Thompson
4c8952de6a Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Thomas Fleming
1294235837 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
Ross Thompson
301166d062 Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Thomas Fleming
8c97143be6 Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Shreya Sanghai
f0ec365117 added performance counters 2021-03-04 11:42:52 -05:00
Teo Ene
6ebb79abe0 Linux CoreMark is operational 2021-03-04 05:58:18 -06:00