changed ideal memory to MEM_DTIM and MEM_ITIM

wally-pipelined/config/buildroot/wally-config.vh

@@ -47,11 +47,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32

wally-pipelined/config/busybear/wally-config.vh

@@ -48,8 +48,9 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.

wally-pipelined/config/coremark/wally-config.vh

@@ -43,16 +43,16 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define DESIGN_COMPILER 0
 
-
 // Microarchitectural Features
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
-`define MEM_VIRTMEM 0
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define MEM_VIRTMEM 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32

wally-pipelined/config/coremark_bare/wally-config.vh

@@ -44,16 +44,16 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define DESIGN_COMPILER 0
 
-
 // Microarchitectural Features
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32

wally-pipelined/config/fpga/wally-config.vh

@@ -47,11 +47,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32

wally-pipelined/config/rv32gc/wally-config.vh

@@ -46,11 +46,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32

wally-pipelined/config/rv32ic/wally-config.vh

@@ -46,11 +46,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32

wally-pipelined/config/rv64BP/wally-config.vh

@@ -48,11 +48,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32

wally-pipelined/config/rv64gc/wally-config.vh

@@ -43,15 +43,16 @@
 `define COUNTERS 32
 `define ZICOUNTERS_SUPPORTED 1
 
-// Microarchitectural Features
+/// Microarchitectural Features
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32

wally-pipelined/config/rv64ic/wally-config.vh

@@ -47,11 +47,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32

wally-pipelined/regression/sim-wally

@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv64g arch64i"
+vsim -do "do wally-pipelined.do rv64gc arch64i"