David Harris
9747d122d2
tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
2023-09-02 12:56:36 -07:00
David Harris
e75ceb044f
Improved tlb and controller coverage; fixed exclusions on broken lines
2023-08-31 00:27:47 -07:00
David Harris
1642ad2bad
Improved NAPOT test coverage
2023-08-30 21:04:36 -07:00
David Harris
91429f3f02
Initial TLB NAPOT tests
2023-08-29 12:39:24 -07:00
David Harris
c45fbe1ffe
Merge pull request #394 from harshinisrinath1001/main
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Improved testing of csri with priv.S!
2023-08-24 19:16:50 -07:00
harshinisrinath
c9112ff18d
Improved testing of csri with priv.S
2023-08-24 18:39:15 -07:00
David Harris
409abbf443
Merge pull request #381 from harshinisrinath1001/main
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Tried to improve coverage of CSRI with priv.S
2023-08-21 13:28:39 -07:00
harshinisrinath
3d3d15077b
cleared stimer interrupt
2023-08-20 15:42:27 -07:00
harshinisrinath
fdb7abec06
tried to improve testing of csri in privileged module
2023-08-20 15:40:02 -07:00
David Harris
2738423441
Improved CSRU coverage with priv.S
2023-08-20 12:49:31 -07:00
harshinisrinath
7494ce06eb
wrote testcase to write into FSCR
2023-08-20 12:10:08 -07:00
harshinisrinath
b4cfdf3393
Fixed bug and tried to reset menvcfg to improve testing of csri in priv.
2023-07-30 16:40:06 -07:00
harshinisrinath
f9d3944cc5
Improved testing of pmd in priv.
2023-06-16 17:13:54 -07:00
harshinisrinath
d018357914
Improve test coverage on ieu fw.
2023-06-16 16:09:48 -07:00
David Harris
f68b9c224a
Fixed WALLY-trap test case to use menvcfg
2023-06-09 15:24:26 -07:00
James Stine
ac3253203d
Update fcvt tests for l.s/lu.s and s.l/s.lu that were missing
2023-06-05 11:03:59 -05:00
Kevin Thomas
0c9b7dcce7
Comment tlbGBL more discriptively
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Reduce redundant instructions
2023-05-04 19:13:47 -05:00
David Harris
ec3518673e
Merge branch 'main' into main
2023-04-28 07:51:32 -07:00
Liam Chalk
028d19bbfa
Merge branch 'main' into main
2023-04-27 21:49:01 -07:00
Kevin Wan
39c9cd5ee9
added tests for pmppriority module
2023-04-27 16:12:43 -07:00
David Harris
15fb5fa2ac
Update tlbASID.S
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fixed comment about restoring ASID to 0
2023-04-27 14:32:57 -07:00
Noah Limpert
4ec31de316
complete camline coverage on IFU and LSU
2023-04-27 14:26:10 -07:00
Liam
4d8eafd27d
Pmpadrdecs test cases changing AdrMode to 2 or 3
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Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
2023-04-27 12:23:35 -07:00
Alexa Wright
09095422d0
Merge branch 'openhwgroup:main' into main
2023-04-26 16:26:30 -07:00
Alexa Wright
59d913949f
Excluded and added coverage for WFI test case.
2023-04-25 17:06:57 -07:00
Liam
7bf2ee5418
pmpaddr0 and pmpaddr2 test cases
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Writing 0x00170000 and 0x17000000 to pmpaddr0 and pmpaddr2.
Increased IFU coverage from 83.53% to 83.68% and LSU coverage from 93.29% to 93.45%.
2023-04-25 15:37:04 -07:00
David Harris
086556310c
Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.
2023-04-22 12:22:45 -07:00
Liam
c2f441724b
pmpcfg test cases
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Increased IFU coverage from 83.37% to 83.53% and LSU coverage from 93.14% to 93.28%.
2023-04-21 20:43:37 -07:00
Noah Limpert
a0e71c26cb
Add in a test that makes match 3 = 0 for all tlb lines
2023-04-20 14:50:06 -07:00
Noah Limpert
7ca44de126
Commiting changes to add coverage to ASID, Global, Megapage size checks.
2023-04-20 14:38:13 -07:00
Liam
4f57dca0dc
Add pmpcfg test cases increasing IFU coverage
2023-04-19 11:58:22 -07:00
David Harris
4cbffd7972
Merge branch 'main' into coverage4
2023-04-19 06:16:07 -07:00
David Harris
b63dff098a
Merge branch 'main' into main
2023-04-19 04:50:12 -07:00
Alec Vercruysse
b3a3af8ed3
add D$ test case to trigger a FlushStage while SetDirtyWay=1
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This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44
Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
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This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
2023-04-19 01:34:01 -07:00
Liam
d74768ce04
Add test cases for pmpcfg.S
2023-04-18 23:06:52 -07:00
Kevin Wan
b5a3ff2d2d
a
2023-04-18 22:09:50 -07:00
Kevin Wan
c91784bd5a
Merge branch 'main' of https://github.com/koooo142857/cvw into main
2023-04-18 21:55:06 -07:00
koooo142857
c9018b8204
Merge branch 'openhwgroup:main' into main
2023-04-18 21:53:46 -07:00
Kevin Wan
771124e265
Completely covers all PMPCFG_ARRAY_REGW cases
2023-04-18 21:50:48 -07:00
Kevin Wan
1bdae2285d
PMPCFG_ARRAY_REGW cases
2023-04-18 18:43:50 -07:00
Miles Cook
5e45fef838
Increase of TLB coverage in IFU
2023-04-17 18:35:03 -07:00
Diego Herrera Vicioso
16fd17be39
Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc
2023-04-15 23:13:39 -07:00
Dygore
cac9c2dc37
Added multiple tests to increase FPU coverage
2023-04-14 14:41:05 -05:00
Dylan
d7936a9214
Merge branch 'openhwgroup:main' into main
2023-04-14 00:36:57 -05:00
Dygore
69b4751162
Added tests for full coverage of the FPU result sign module
2023-04-14 00:36:12 -05:00
Noah Limpert
6a23bbea9d
add back K. Box and M. Cook Lsu test
2023-04-13 17:50:18 -07:00
Noah Limpert
3683139637
make pull request more clean
2023-04-13 17:44:09 -07:00
Noah Limpert
b35d5bdbdb
Revert "instantiate 5 4KiB arrays, aim to thrash all 4 ways"
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This reverts commit 6acf1dadda
2023-04-13 17:40:39 -07:00
Noah Limpert
d012715a60
Revert "Test File for Pull Request, Attempt to fill all four ways"
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This reverts commit e887341c80
2023-04-13 17:28:37 -07:00
