David Harris
|
363b7f56a5
|
Merge pull request #61 from mmasserfrye/main
USE_SRAM parameter, makefile config cleaning
|
2023-02-04 03:28:44 -08:00 |
|
Madeleine Masser-Frye
|
7b0da71297
|
finishing the job of the last commit
|
2023-02-04 10:24:01 +00:00 |
|
Madeleine Masser-Frye
|
d9e1323e57
|
added use sram parameter, cleaned up config writing, added single synth functionality to wallySynth
|
2023-02-04 09:50:36 +00:00 |
|
David Harris
|
d4a7679926
|
Merge pull request #60 from ross144/main
Optimized PCLink logic.
|
2023-02-03 16:42:27 -08:00 |
|
Ross Thompson
|
c4a9354c13
|
Replaced PCLinkX registers with a +2/4 adder in the execution stage.
David and I estimate this is lower hardware cost.
|
2023-02-03 18:19:47 -06:00 |
|
Ross Thompson
|
6dcce8389a
|
Change CurrPtr to Ptr in RAS.
|
2023-02-03 17:40:20 -06:00 |
|
David Harris
|
02bdaf858c
|
Merge pull request #54 from ross144/main
Fixed issue #50, itlb and dcache flush interlock
|
2023-02-03 06:30:30 -08:00 |
|
Ross Thompson
|
370931c1cd
|
Fixed bug #49.
FFLAGS was updated while the pipeline was stalled.
Also I found serveral performance counters which had similar issues.
|
2023-02-03 00:39:26 -06:00 |
|
Ross Thompson
|
a4907b5d29
|
Lee Moore found another bug using imperas.
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
|
2023-02-02 23:52:21 -06:00 |
|
David Harris
|
be618a0c34
|
Update README.md
|
2023-02-02 12:59:28 -08:00 |
|
James E. Stine
|
2a87495642
|
Merge pull request #52 from stineje/main
Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
|
2023-02-02 13:55:17 -06:00 |
|
James Stine
|
bfa69ea2b3
|
Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
|
2023-02-02 13:54:25 -06:00 |
|
David Harris
|
4c50166e56
|
Merge pull request #51 from stineje/main
Modify generic/mem for rv32gc ram2
|
2023-02-02 11:41:32 -08:00 |
|
James Stine
|
b66177fd87
|
Modify generic/mem for rv32gc ram2
|
2023-02-02 13:28:18 -06:00 |
|
David Harris
|
bc0ca38b2f
|
Merge pull request #48 from ross144/main
Fixed bug #47, ecall and ebreak don't commit
|
2023-02-02 06:58:07 -08:00 |
|
Ross Thompson
|
091aadff0e
|
Merge branch 'main' of github.com:ross144/cvw
|
2023-02-02 08:52:48 -06:00 |
|
Ross Thompson
|
230888db8b
|
Fixed bug #47 discovered by Lee Moore.
ECALL and EBREAK do not commit their results.
|
2023-02-02 08:52:06 -06:00 |
|
Ross Thompson
|
d62a72a76f
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
|
2023-02-02 08:48:19 -06:00 |
|
Ross Thompson
|
a8afdf1741
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2023-02-01 19:24:10 -06:00 |
|
David Harris
|
c214a9e8fc
|
Merge pull request #45 from stineje/main
Update ram2 and other memories and associated wrappers
|
2023-02-01 15:06:30 -08:00 |
|
James Stine
|
6ce80b6b8a
|
Update ram2 and other memories and associated wrappers
|
2023-02-01 17:03:48 -06:00 |
|
Ross Thompson
|
0035579553
|
Minor branch predictor bug fix.
|
2023-02-01 10:59:38 -06:00 |
|
Ross Thompson
|
2a5b6408f2
|
Removed unused signal.
|
2023-02-01 10:27:58 -06:00 |
|
David Harris
|
73b29e1f71
|
Merge pull request #36 from davidharrishmc/dev
RV32imc configuration
|
2023-02-01 04:44:36 -08:00 |
|
David Harris
|
0280942563
|
Fixed merge conflict to get synthesis working again
|
2023-02-01 04:43:57 -08:00 |
|
David Harris
|
838bb21077
|
Merge pull request #43 from mmasserfrye/main
ram size, bpred size, memories *SYNTH NOT FUNCTIONAL*
|
2023-02-01 04:13:37 -08:00 |
|
Ross Thompson
|
c3e3afe398
|
Minor change to btb.
|
2023-02-01 00:24:54 -06:00 |
|
Madeleine Masser-Frye
|
ad6d7eb5e2
|
added memories (not tested)
|
2023-02-01 06:08:27 +00:00 |
|
Ross Thompson
|
a9624b1413
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2023-02-01 00:01:14 -06:00 |
|
Madeleine Masser-Frye
|
c78adbb8e7
|
increased bpred size to (2^) 5
|
2023-02-01 05:51:31 +00:00 |
|
Madeleine Masser-Frye
|
02a1432c46
|
updated synth makefile to change all relevant
ram ranges to 1FF
|
2023-02-01 05:40:35 +00:00 |
|
Madeleine Masser-Frye
|
a8ed39ecbe
|
Merge branch 'main' of https://github.com/mmasserfrye/cvw
|
2023-02-01 05:23:04 +00:00 |
|
Ross Thompson
|
8a6eaa23cc
|
Minor optimization to btb.
|
2023-01-31 22:03:51 -06:00 |
|
David Harris
|
c666015c56
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-01-31 14:40:19 -08:00 |
|
David Harris
|
9270285f3a
|
Removed student solution to fir
|
2023-01-31 14:40:12 -08:00 |
|
David Harris
|
8d242d47dd
|
Merge pull request #42 from ross144/main
Scripts to run imperas
|
2023-01-31 14:31:10 -08:00 |
|
Ross Thompson
|
81b280576f
|
Updates to RAS.
|
2023-01-31 15:17:32 -06:00 |
|
Ross Thompson
|
fc2e3fed91
|
Simplified RAS.
|
2023-01-31 14:54:05 -06:00 |
|
Ross Thompson
|
a89f9dc92c
|
RAS file name was spelled wrong.
|
2023-01-31 14:35:05 -06:00 |
|
Ross Thompson
|
92fc532b82
|
Created scripts to install imperas and run a single test using imperas.
|
2023-01-31 13:51:05 -06:00 |
|
David Harris
|
ce98083ffd
|
Merge pull request #41 from ross144/main
Merged imperas branch into main. Remove old branch when pull request accepted.
|
2023-01-31 11:35:50 -08:00 |
|
Ross Thompson
|
d821105697
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2023-01-31 13:04:41 -06:00 |
|
Ross Thompson
|
c9c4f63c18
|
Fixed remaining bugs in the imperas merge.
|
2023-01-31 13:04:26 -06:00 |
|
Ross Thompson
|
026071e247
|
Merge branch 'imperas'
|
2023-01-31 12:46:22 -06:00 |
|
Ross Thompson
|
5a770f148c
|
Minor bug fix in gshare.
|
2023-01-31 10:45:32 -06:00 |
|
Ross Thompson
|
ad0a0f0d51
|
Renamed signals in RAS.
|
2023-01-31 10:44:11 -06:00 |
|
David Harris
|
e96ba254eb
|
Removed output delay in synthesis
|
2023-01-31 04:37:23 -08:00 |
|
Ross Thompson
|
0e3c77bed3
|
Found small bug in gshare.
|
2023-01-31 00:17:49 -06:00 |
|
Ross Thompson
|
939095615f
|
Fixed parameterization in testbench.
|
2023-01-31 00:11:01 -06:00 |
|
Ross Thompson
|
8feac6d242
|
Parameterized testbench branch predictor preload.
|
2023-01-31 00:08:11 -06:00 |
|