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3623dfa51e
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Author SHA1 Message Date
Kip Macsai-Goren
3623dfa51e removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions. 2021-10-08 15:33:18 -07:00
Kip Macsai-Goren
3cb5ebd165 updated pmpaddr values, test library to remove unused and unneeded tests. 2021-10-08 15:29:32 -07:00
David Harris
7e340d16fd moved fp vectors into vectors subdirectory 2021-10-07 23:28:06 -04:00
David Harris
626780381a Included TestFloat and SoftFloat 2021-10-07 23:03:45 -04:00
bbracker
64a3043a88 update wave-do 2021-10-07 19:16:52 -04:00
bbracker
25e0745a6a fix div restarting bug 2021-10-07 18:55:00 -04:00
James E. Stine
0c408a9816 update scripts 2021-10-07 15:14:54 -05:00
bbracker
ec1e04e8b8 update linker scripts to look for vmlinux files 2021-10-06 16:55:38 -04:00
James E. Stine
4dcfcfacfc TV for conversion and compare 2021-10-06 14:38:32 -05:00
James E. Stine
739e17ddac Add generic wave command file 2021-10-06 13:17:49 -05:00
James E. Stine
54786a4fef Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-06 13:16:49 -05:00
James E. Stine
658dcc8c1b Update to testbench for FP stuff 2021-10-06 13:16:38 -05:00
Teo Ene
8af155ed94 Removed instances of <U+200B> character from synth script 2021-10-06 13:11:09 -05:00
James E. Stine
4ece7b5341 Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included 2021-10-06 08:56:01 -05:00
James E. Stine
b90d7b8083 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
Skylar Litz
a924e79e26 added delayed MIP signal 2021-10-04 18:23:31 -04:00
David Harris
cc41d40d61 Divider cleaup 2021-10-03 11:22:34 -04:00
David Harris
3398328bf1 Divider cleanup 2021-10-03 11:16:48 -04:00
David Harris
9809e57d0c Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
bf0061be66 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
bd61ec544b Divider comments cleanup 2021-10-03 01:12:40 -04:00
David Harris
30ec68d567 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
a15068717b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-03 00:43:47 -04:00
David Harris
078ddfd341 Divider cleanup 2021-10-03 00:41:41 -04:00
David Harris
8f36297569 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
bbracker
07ff0940a3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-03 00:30:49 -04:00
bbracker
a202c705cd checkpoint generator bugfixes 2021-10-03 00:30:04 -04:00
David Harris
dcbbee6623 More divider cleanup 2021-10-03 00:20:35 -04:00
David Harris
6aa2521959 Eliminated extra inversion for subtraction in divider 2021-10-03 00:10:12 -04:00
David Harris
371f9d9a4a Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
24bb3f4baf Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
3441991d93 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
67690c2ed7 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
775520c05a Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
fe69513bb7 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
a86ce5cd37 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
d532bde931 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
d4437b842a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
735132191c Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
David Harris
73d852b1ef Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
35e5a5cef3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
bbracker
5022647041 Revert "first attempt at verilog side of checkpoint functionality" 
This reverts commit f6ef8e5656.
 2021-09-30 20:45:26 -04:00
David Harris
a39e14663d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 20:07:43 -04:00
David Harris
a8573a27d4 Integer Divide/Rem passing all regression. 2021-09-30 20:07:22 -04:00
David Harris
953c8931ed RV32 div/rem working signed and unsigned 2021-09-30 15:24:43 -04:00
David Harris
e1ad732178 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
bbracker
f6ef8e5656 first attempt at verilog side of checkpoint functionality 2021-09-28 23:17:58 -04:00
bbracker
a47448c4d0 first attemtpt at checkpoint infrastructure 2021-09-28 22:33:47 -04:00
bbracker
2ffdbdf6d2 condense testbench code; debug_level of 0 means don't check at all 2021-09-27 03:03:11 -04:00