Ross Thompson
bc437cf7e0
Cleaned up some names in dcache and lsu.
2021-12-29 11:21:44 -06:00
Ross Thompson
fe22d4544f
Converted mux4 to mux3 in dcache.
2021-12-29 10:58:02 -06:00
Ross Thompson
0c88ddeb5a
Simplified the dcache to bus address generation.
2021-12-29 10:46:48 -06:00
Ross Thompson
6052a69ba7
Fixed interrupt delay bug by reverting CommittedM changes.
2021-12-28 22:27:12 -06:00
Ross Thompson
1894afd0d8
Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters.
...
Fixed bug with the uncached memory operations. The periph tests still do not pass. They enter into what seems an intentional infinite loop. Then a uart interrupt jumps into an ISR but the ISR returns back to the loop.
2021-12-28 21:28:03 -06:00
Ross Thompson
76d1dc1721
LSU Bus FSM beautification.
2021-12-28 16:53:53 -06:00
Ross Thompson
e29803be30
Removed CommittedM as it is redundant with LSUStall.
2021-12-28 16:14:10 -06:00
Ross Thompson
39bd78c295
Changed the bus name between dcache and ebu.
2021-12-28 15:57:36 -06:00
Ross Thompson
d62cd1f701
Reverted changes to subwordread while keeping the new names of the i/o.
2021-12-28 15:57:21 -06:00
Ross Thompson
9c190b019b
Name changes for states in LSU.
2021-12-28 15:03:24 -06:00
Ross Thompson
13b4201198
Added generate around virtual memory hardware in LSU.
2021-12-28 15:00:02 -06:00
Ross Thompson
f09b10a393
Moved generate for lrsc to lsu.
2021-12-28 14:17:18 -06:00
Ross Thompson
73af458eb5
More cleanup of dcache.
2021-12-28 14:12:18 -06:00
Ross Thompson
0e86e5d9f1
Additional cleanup of the LSU.
2021-12-28 13:59:07 -06:00
Ross Thompson
1e76c24f26
Major cleanup of the LSU.
2021-12-28 13:10:45 -06:00
Ross Thompson
79b17c5b55
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
Ross Thompson
34c11ca8d5
Minor dcache cleanup.
2021-12-28 11:29:16 -06:00
Ross Thompson
243728d089
Moved all bus logic outside the dcache. Still needs cleanup.
2021-12-28 11:18:47 -06:00
Ross Thompson
74d636cb53
First cut at moving the dcache bus interface into the LSU.
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Regression test does not run and there is a lot of cleanup to do.
2021-12-27 18:12:59 -06:00
Ross Thompson
d366a1f50f
Moved dcache fetch logic outside the dcache except for the fsm.
2021-12-27 16:45:49 -06:00
Ross Thompson
e3ddcbb11e
Partial commit.
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Moved AMO, SWW, and SWR outside the dcache.
Step 1 of separate the fetching logic from the caches.
2021-12-27 15:56:18 -06:00
Ross Thompson
7fe70c3cc6
Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.
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1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.
There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop
for each TLB line.
2021-12-23 12:40:22 -06:00
Ross Thompson
6a8e917e06
It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.
2021-12-21 15:59:56 -06:00
Ross Thompson
7844d3f064
Fixed bug where the wrong address is read into the icache memory.
2021-12-21 15:16:00 -06:00
Ross Thompson
8b97aaac3e
Fixed complex bug where FENCE is instruction class miss predicted as a taken branch.
2021-12-21 11:29:28 -06:00
Ross Thompson
3f62a64056
Identified bug in the IFU which selects PCNextF when InvalidateICacheM is true. If the ID is invalid PCNextF should NOT be PCE.
2021-12-20 23:45:55 -06:00
Ross Thompson
a157235a4b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 23:27:46 -06:00
Ross Thompson
ffe792bcfc
Fixed bug on icache spill. if the cpu stalled on the completion it was possible to use the wrong address for the sram read. Also miss spill hit always selected the wrong address.
2021-12-20 23:27:37 -06:00
David Harris
bf9082b0ad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-20 21:09:20 -08:00
David Harris
475fa01767
Fixing paths in wally-setup.sh
2021-12-20 21:08:34 -08:00
Ross Thompson
8416cae3fe
Fixed Type 5b interaction between dcache and hptw.
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This is a load concurrent with ITLBMiss.
2021-12-20 18:33:31 -06:00
Ross Thompson
b6d75d453a
Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM.
2021-12-20 10:03:56 -06:00
Ross Thompson
beb1988539
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
df8bd78679
More signal name cleanup in LSU.
2021-12-19 22:47:48 -06:00
Ross Thompson
3eb5f33705
Remove verbosity from lsu state machine.
2021-12-19 22:41:34 -06:00
Ross Thompson
d3c3422d12
Rename of SelPTW to SelHPTW.
2021-12-19 22:24:07 -06:00
Ross Thompson
8feb36b926
Signal renames.
2021-12-19 22:21:03 -06:00
Ross Thompson
dc82d44f9e
Hardware reductions in the lsu.
2021-12-19 22:00:28 -06:00
Ross Thompson
dc95896303
Removed HPTWStall. Not needed as InterlockStall from the LSU provides the equivalent.
2021-12-19 21:36:54 -06:00
Ross Thompson
138da1fefa
Removed lsuArb and placed remaining logic in lsu.sv.
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Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
2021-12-19 21:34:40 -06:00
David Harris
a25d541dcf
Moved generate of conditional units to hart
2021-12-19 17:03:57 -08:00
David Harris
3c3bfd055e
Moved generate statements for optional units into wallypipelinedhart
2021-12-19 16:53:41 -08:00
Ross Thompson
32a4afc7a1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-19 18:16:49 -06:00
Ross Thompson
a39b47d226
Switched to using an always block for lsu stall logic. This avoids the problematic x propagation.
2021-12-19 18:16:08 -06:00
Ross Thompson
eceb418056
Implemented what I think is the last required change for the lsu state machine.
2021-12-19 17:57:12 -06:00
Ross Thompson
fe5c05eb8d
Created hack to get around imperas64mmu unknown (value = x) bug.
2021-12-19 17:53:13 -06:00
Ross Thompson
c453b285dc
Fixed bug where icache did not replay PCF on itlb miss.
2021-12-19 17:01:13 -06:00
Ross Thompson
c9291655da
Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
2021-12-19 16:12:31 -06:00
David Harris
53cd2ac049
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-19 13:53:53 -08:00
David Harris
9e6c9c38c0
ALUControl cleanup
2021-12-19 13:53:45 -08:00
Katherine Parry
e3f2a252cd
fixed some small errors in FMA
2021-12-19 13:51:46 -08:00
Ross Thompson
f4d778c2f6
Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm.
2021-12-19 15:10:33 -06:00
Ross Thompson
a445bedcd2
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
...
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
225cd5a114
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
cd3c1032b7
Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states.
2021-12-19 13:55:57 -06:00
Ross Thompson
1126135b80
minro change. comments about needed changes in dcache.
2021-12-19 13:53:02 -06:00
David Harris
f201af4bb7
Renamed zero to eq in flag generation
2021-12-19 11:49:15 -08:00
David Harris
406f129bed
Controller fix
2021-12-18 22:08:23 -08:00
David Harris
67577d7c91
Renamed RD1D to R1D, etc.
2021-12-18 21:26:00 -08:00
David Harris
721d0b5bcf
Simplified shifter right input
2021-12-18 10:25:40 -08:00
Ross Thompson
4daeb6657f
Merge branch 'tlb_fixes' into main
2021-12-18 12:24:17 -06:00
David Harris
7e026f3e78
Simplified Shifter Right input
2021-12-18 10:21:17 -08:00
David Harris
27ec8ff893
Shared ALU mux input for shifts
2021-12-18 10:08:52 -08:00
David Harris
eed2765033
Factored out common parts of shifter
2021-12-18 10:01:12 -08:00
David Harris
53baf3e787
Cleaning shifter
2021-12-18 09:43:09 -08:00
David Harris
ebcffcdebd
Moved W64 truncation after result mux
2021-12-18 09:27:25 -08:00
David Harris
23c6b6370f
Forwarding logic factoring
2021-12-18 05:40:38 -08:00
David Harris
10dfefa8ad
Simplified FWriteInt interfaces by merging into RegWrite
2021-12-18 05:36:32 -08:00
Ross Thompson
bbd1332353
Merge remote-tracking branch 'origin/tlb_fixes' into main
2021-12-17 14:40:29 -06:00
Ross Thompson
a11597b6bd
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
ee81cfff0c
Possible fix for icache deadlock interaction with hptw.
2021-12-17 14:38:25 -06:00
David Harris
aebd746e71
Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
2021-12-15 12:10:45 -08:00
David Harris
4e35736e90
IEU cleanup:
2021-12-15 11:38:26 -08:00
Ross Thompson
6d2a4b8354
Oups missed files in the last commit.
2021-12-15 10:25:08 -06:00
David Harris
865d5ce0b1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
Ross Thompson
9886ed3028
Comments for dcache and icache refactoring.
2021-12-14 14:46:29 -06:00
David Harris
0e9fe6c214
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-14 11:15:58 -08:00
David Harris
2d24230093
ALU and datapath cleanup
2021-12-14 11:15:47 -08:00
Ross Thompson
af9f97454d
Cleaned up fpga synthesis script.
2021-12-13 18:26:54 -06:00
Ross Thompson
2d662bc4be
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-13 17:16:20 -06:00
Ross Thompson
81da8b8d2a
Formating changes to cache fsms.
2021-12-13 17:16:13 -06:00
Ross Thompson
4d6d72a082
Fixed some typos in the dcache ptw interaction documentation.
2021-12-13 15:47:20 -06:00
David Harris
55f3979b67
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-13 07:57:49 -08:00
David Harris
2039752740
Simplified ALU and source multiplexers pass tests
2021-12-13 07:57:38 -08:00
kwan
8f79a12cbb
priviledge .* removed, passed regression
2021-12-13 00:34:43 -08:00
kwan
f0e425e4ea
test
2021-12-13 00:31:51 -08:00
kwan
a365e86197
priviledge .* fixed, passed local regression
2021-12-13 00:22:01 -08:00
Ross Thompson
051dd7d09d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-12 17:33:29 -06:00
Ross Thompson
395766219b
Revert "Privilige .*s removed"
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This reverts commit 82bab8e90e
2021-12-12 17:31:57 -06:00
Ross Thompson
f758a53247
Revert "Priviledged .* removed"
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This reverts commit a95efea0b3
2021-12-12 17:31:39 -06:00
Ross Thompson
39168a201b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-12 17:21:51 -06:00
Ross Thompson
68745d40f2
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
2021-12-12 17:21:44 -06:00
Ross Thompson
545c586186
Added proper credit to Richard Davis, the author of the original sd card reader.
2021-12-12 15:05:50 -06:00
kwan
a95efea0b3
Priviledged .* removed
2021-12-12 09:55:45 -08:00
kwan
82bab8e90e
Privilige .*s removed
2021-12-12 09:54:14 -08:00
David Harris
a7e9dee77d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-12 05:49:31 -08:00
Ross Thompson
37079626cd
Fixed numerous errors in the preformance counter updates.
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Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
2021-12-09 11:44:12 -06:00
slmnemo
e39f94b645
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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help
2021-12-08 14:09:58 -08:00
slmnemo
f2f15c0495
Removed .* from /wally-pipelined/src/uncore/uart.sv
2021-12-08 14:02:53 -08:00
Ross Thompson
f1ea52cb2d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-08 15:50:43 -06:00
