David Harris
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dea2ec280e
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testgen-PIPELINE python startup
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2021-03-25 13:12:18 -04:00 |
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Shriya Nadgauda
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e55a245948
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adding PIPELINE tests
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2021-03-25 13:07:25 -04:00 |
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Jarred Allen
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fdecd6c56c
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Clean up some stuff
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2021-03-25 13:04:54 -04:00 |
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Jarred Allen
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15e786da0b
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Working for all of rv64i now, but not compressed instructions
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2021-03-25 13:02:26 -04:00 |
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Jarred Allen
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e8e4e1bee2
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rv64i linear control flow now working
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2021-03-25 13:02:26 -04:00 |
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Jarred Allen
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08f4ce4438
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More progress on icache controller
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2021-03-25 13:01:11 -04:00 |
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Jarred Allen
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fff70bccbc
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Begin rewrite of icache module to use a direct-mapped scheme
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2021-03-25 13:01:10 -04:00 |
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Jarred Allen
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5a86225e1c
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Fix bug in cache line
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2021-03-25 12:59:30 -04:00 |
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Jarred Allen
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abedaf62a8
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Output NOP instead of BAD when reset
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2021-03-25 12:42:48 -04:00 |
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Jarred Allen
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2f5d854f87
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Merge branch 'main' into cache
Conflicts:
wally-pipelined/src/uncore/dtim.sv
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2021-03-25 12:10:26 -04:00 |
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Teo Ene
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7c3963547d
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Config file for ppa experiments
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2021-03-25 10:23:21 -05:00 |
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David Harris
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1158b3aa73
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Added PPA README
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2021-03-25 11:21:31 -04:00 |
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Thomas Fleming
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89a2fe5741
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Finish finite state machines for page table walker
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2021-03-25 02:48:40 -04:00 |
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Thomas Fleming
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95bf1e26b8
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Add vscode and pycache folders to .gitignore
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2021-03-25 02:37:50 -04:00 |
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Thomas Fleming
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4f01aae844
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-03-25 02:35:21 -04:00 |
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bbracker
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d52c71086a
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added 1 tick delay to dtim flops
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2021-03-25 02:23:30 -04:00 |
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bbracker
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ca392225df
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added 1 tick delay on tim reads
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2021-03-25 02:15:28 -04:00 |
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Jarred Allen
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9cbdb44728
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Merge branch 'main' into cache
Conflicts:
wally-pipelined/src/ifu/ifu.sv
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2021-03-25 00:51:12 -04:00 |
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bbracker
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6edb055f26
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instrfault direspecting stalls bugfix
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2021-03-25 00:44:35 -04:00 |
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bbracker
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5327dcfcc8
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instrfaults not respecting stalls bugfix
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2021-03-25 00:16:26 -04:00 |
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bbracker
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a8b7d7a248
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upgraded gpio bus interface
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2021-03-25 00:15:02 -04:00 |
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bbracker
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77768cee5d
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gitignore FunctionRadix.addr
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2021-03-25 00:13:46 -04:00 |
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bbracker
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3e656fc035
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future work comment about suspicious-looking verilog in csri.sv
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2021-03-25 00:10:44 -04:00 |
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Thomas Fleming
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f2604797fb
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Add all PMP addr registers
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2021-03-24 21:58:33 -04:00 |
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Teo Ene
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55c5d2ca23
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Manual assembly hack to prevent RV64IM coremark from EBREAKing early
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2021-03-24 18:05:34 -05:00 |
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Teo Ene
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1e691e120b
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Fix typo from last commit
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2021-03-24 17:09:58 -05:00 |
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Teo Ene
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9f44eb36ef
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-03-24 17:04:48 -05:00 |
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Teo Ene
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6a7b69ff2d
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Updated coremark_bare testbench for IM
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2021-03-24 17:04:43 -05:00 |
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Katherine Parry
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123e63b440
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fixed various bugs in the FMA
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2021-03-24 21:51:17 +00:00 |
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Teo Ene
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07f7df82e3
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Added BPTYPE to coremark_bare config
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2021-03-24 16:38:29 -05:00 |
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Ross Thompson
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cdb7d15709
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Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
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2021-03-24 15:56:55 -05:00 |
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Ross Thompson
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a768c0406c
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Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed.
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2021-03-24 13:03:43 -05:00 |
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Domenico Ottolia
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3909158619
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re-organize privileged tests to be in rv64p to rv32p folders
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2021-03-24 13:51:25 -04:00 |
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Jarred Allen
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0776127c75
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Give some cache mem inputs a better name
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2021-03-24 12:31:50 -04:00 |
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Ross Thompson
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754f55c564
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Updated the .gitignore to reject all the extra compiled objects for the branchmarks.
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2021-03-24 10:30:19 -05:00 |
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Ross Thompson
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58487db60a
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Edited sieve to work with wally. It was using the time of day to compute runspeed; however this functionality does not yet work in the wally software stack.
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2021-03-24 09:22:21 -05:00 |
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Jarred Allen
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abf9f3b3cb
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Fix compile errors from const not actually being constant (why does Verilog do this)
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2021-03-24 00:58:56 -04:00 |
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Ross Thompson
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ace39940b4
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Fixed RAS errors. Still some room for improvement with the BTB and RAS.
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2021-03-23 23:00:44 -05:00 |
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Jarred Allen
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1f01a12be9
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Merge branch 'main' into cache
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2021-03-23 23:35:36 -04:00 |
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Ross Thompson
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72d25d4443
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Fixed a bunch of bugs with the RAS.
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2021-03-23 21:49:16 -05:00 |
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Katherine Parry
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fb78dedae2
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fixed various bugs in the FMA
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2021-03-24 01:35:32 +00:00 |
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Ross Thompson
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c318606f05
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Fixed the valid bit issue. Now the branch predictor is actually predicting instructions.
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2021-03-23 20:20:23 -05:00 |
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Ross Thompson
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9d5c351340
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fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.
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2021-03-23 20:06:45 -05:00 |
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Ross Thompson
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dee5d16850
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fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled.
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2021-03-23 16:53:48 -05:00 |
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Jarred Allen
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ebd2c60b74
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Begin work on direct-mapped cache
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2021-03-23 17:03:02 -04:00 |
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Teo Ene
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8556c07261
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Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem
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2021-03-23 15:21:13 -05:00 |
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Ross Thompson
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4836e8fe2c
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Simulation definitely shows the branch predictor counters and branch predictor don't work. :(
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2021-03-23 14:04:58 -05:00 |
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Ross Thompson
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c7e34bd4a0
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added a whole bunch of interseting test code for branches which does not work.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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c4f7c65210
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updated the branch predictor config.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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9909bdd4d5
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Added first benchmark.
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2021-03-23 13:54:59 -05:00 |
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