30 Commits

Author	SHA1	Message	Date
slmnemo	75dffe4dcc	Merge branch 'main' into cacheburstmode	2022-06-09 17:51:03 -07:00
David Harris	5612ca7041	qslc_r4a2 generator	2022-06-09 17:26:47 +00:00
slmnemo	a64e65e54c	Fixed ifu displaying LSU bus state in wave.do	2022-06-08 15:30:32 -07:00
DTowersM	abb6ba97cf	removed delapidated signals SIE_REGW SIP_REGW TimerIntM SwIntM	2022-05-31 20:10:56 +00:00
bbracker	cbff9a7755	expand WALLY-PERIPH test to use SEIP on PLIC context 1	2022-03-31 18:02:06 -07:00
bbracker	c1290d493f	add CSRs to waveview	2022-03-02 18:31:10 +00:00
bbracker	6caa97bb26	change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests	2022-02-22 03:46:08 +00:00
Ross Thompson	2fc7dc3e57	Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.	2022-02-17 10:04:18 -06:00
Ross Thompson	62f5f1e622	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
Ross Thompson	a440bc2ac5	More cache cleanup.	2022-02-13 15:47:27 -06:00
Ross Thompson	1e7e59bdbd	Changed names of signals in cache.	2022-02-13 15:06:18 -06:00
Ross Thompson	9ad4523b9d	Updated wave files to reflect recent changes.	2022-02-10 17:52:19 -06:00
David Harris	e92461159d	cache cleanup	2022-02-03 15:36:11 +00:00
Ross Thompson	88a408b3e6	Added helpful signals to wavefile. ... Makefile for tests now creates the function address to name mapping files. The function name and test name are included in the wave file.	2022-02-02 10:15:54 -06:00
Ross Thompson	058b368a22	Improved function_radix to not printout warnings when no valid function is found.	2022-02-01 18:03:09 -06:00
Ross Thompson	138b17a399	Setup the main regression test to be able to handle coremark.	2022-02-01 17:00:11 -06:00
Ross Thompson	3475e142a5	Repaired wavefile and fixed modelsim warning.	2022-01-31 12:34:17 -06:00
Ross Thompson	de0bef4f5b	Updated wave.do to match the ifu/lsu changes.	2022-01-28 14:37:15 -06:00
Ross Thompson	1bb8d36308	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
David Harris	ca1f7ce5d3	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	f7f3882cb8	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
David Harris	d9e8d16bbe	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
Ross Thompson	861450c4d6	Fixed support to allow spills and no icache.	2022-01-12 17:25:16 -06:00
Ross Thompson	87485f9f64	Improve wavefile by adding performance counters.	2022-01-12 10:53:29 -06:00
Ross Thompson	55456e465c	Added icache access and icache miss to performance counters.	2022-01-09 22:56:56 -06:00
Ross Thompson	e01c8bc5f6	Added performance counters to wavefile.	2022-01-09 22:42:14 -06:00
Ross Thompson	3109fa1383	Fixed wavefile. ... Converted coremark to use elf2hex.	2022-01-09 22:03:10 -06:00
Ross Thompson	0310df96a4	Changes to wave file.	2022-01-05 14:16:59 -06:00
Ross Thompson	888a60d8d6	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00