Rose Thompson
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33b123aa25
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Added cbop to to rv32gc.
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2023-11-14 10:55:22 -06:00 |
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Rose Thompson
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508c0cb188
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Fixed another bug in the updated script changes.
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2023-11-13 18:12:02 -06:00 |
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Rose Thompson
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a5303d25aa
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-13 18:10:35 -06:00 |
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Rose Thompson
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04cda8cb71
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Fixed bugs in the updated fpga synthe script.
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2023-11-13 18:10:22 -06:00 |
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Rose Thompson
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4302c0a3b0
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Removed fpga config. No longer needed.
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2023-11-13 17:50:29 -06:00 |
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Rose Thompson
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7f2d03df7f
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Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
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2023-11-13 17:48:28 -06:00 |
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Rose Thompson
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b81bd35724
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Towards removing the FPGA config file.
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2023-11-13 17:20:26 -06:00 |
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Rose Thompson
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e7cf9de469
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Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.
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2023-11-13 16:44:02 -06:00 |
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Rose Thompson
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ed7829dba8
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Fixed bug in uncore updates which broke SDC.
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2023-11-13 16:15:23 -06:00 |
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Rose Thompson
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3a495f2552
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Cleanup and optimization of Zicclsm.
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2023-11-13 14:28:22 -06:00 |
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Rose Thompson
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a53b9403e2
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Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.
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2023-11-13 14:12:27 -06:00 |
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Rose Thompson
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17768471f8
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Cleanup.
Linux makefile
wally tracer. probably reduce some complexity here.
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2023-11-13 14:04:43 -06:00 |
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Rose Thompson
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2f7479966b
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Merge branch 'Zicclsm'
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2023-11-13 13:53:42 -06:00 |
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Rose Thompson
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b813fe8061
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Updates to linux config files for sdc.
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2023-11-13 13:53:23 -06:00 |
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Rose Thompson
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7ff89380e0
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Updated buildroot to use kernel 6.6 and added dedicated qemu emulation script.
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2023-11-13 12:36:32 -06:00 |
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Rose Thompson
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8860aa9af5
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Cleanup.
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2023-11-13 12:35:11 -06:00 |
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Rose Thompson
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534538b216
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Simplification.
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2023-11-10 18:39:36 -06:00 |
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Rose Thompson
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7158aa8390
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Yay! Zicclsm passes my regression test now.
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2023-11-10 18:28:51 -06:00 |
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Rose Thompson
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c29ef1666b
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Found another bug in the RTL's Zicclsm alignment.
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2023-11-10 18:26:55 -06:00 |
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Rose Thompson
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fa6e53d8cf
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Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
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2023-11-10 17:58:42 -06:00 |
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Rose Thompson
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2491ef0e23
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Fixed some more bugs in the Zicclsm signature.
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2023-11-10 17:36:10 -06:00 |
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Rose Thompson
|
3245e2a99e
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Fixed bug in the Zicclsm test.
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2023-11-10 17:34:23 -06:00 |
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Rose Thompson
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bd9a750583
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Fixed spill bugs in the aligner.
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2023-11-10 17:18:45 -06:00 |
|
Rose Thompson
|
b555620ac8
|
Fixed bug in the misaligned access test.
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2023-11-10 17:02:15 -06:00 |
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Rose Thompson
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4b24878053
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Merge branch 'main' into Zicclsm
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2023-11-10 16:15:32 -06:00 |
|
Rose Thompson
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329f4456b0
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Missed tests.vh.
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2023-11-10 16:10:10 -06:00 |
|
Rose Thompson
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89bf1a5cf9
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Fixed bug which broke the non Zicclsm configs.
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2023-11-10 16:08:04 -06:00 |
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Rose Thompson
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5026772301
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Merge pull request #463 from davidharrishmc/dev
Dev
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2023-11-10 08:48:07 -08:00 |
|
David Harris
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68115c6d6b
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Imperas commenting
|
2023-11-10 08:26:32 -08:00 |
|
David Harris
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ae769e90aa
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Add Svadu support and SPI to imperas configuration
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2023-11-10 06:27:25 -08:00 |
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David Harris
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5dbe869339
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Merge pull request #460 from naichewa/main
removed vestigial logic, added comments, deleted unused signals
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2023-11-10 05:18:57 -08:00 |
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naichewa
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fd06472de8
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Cleanup
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2023-11-09 16:52:55 -08:00 |
|
naichewa
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2b4cf01a21
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Remove old 2/4 bit logic, add comments,
clean up unused signals
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2023-11-09 16:48:11 -08:00 |
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David Harris
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1876d5bebf
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-09 10:33:25 -08:00 |
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Rose Thompson
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89a303fbef
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Merge pull request #458 from stineje/main
fix to setup.csh and also ppaSynth.py
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2023-11-09 10:20:05 -08:00 |
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David Harris
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d1e73ee9c2
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Reporting stall path in synthesis script, support Zcb in Imperas
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2023-11-09 06:59:29 -08:00 |
|
James E. Stine
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29d6fe8fea
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update README on ppa
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2023-11-09 01:00:33 -06:00 |
|
James E. Stine
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20e1e12234
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update ppaSynth.py with runCommand
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2023-11-09 00:52:40 -06:00 |
|
James E. Stine
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5361766045
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Add encoding for utf-8 on wrapperGen.py to avoid issue with incorrect encoding on RHEL C-shell
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2023-11-08 23:57:59 -06:00 |
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David Harris
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917af1e988
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-08 16:06:50 -08:00 |
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David Harris
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01d24b3505
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Merge pull request #459 from naichewa/main
hardware interlock and hold mode fixes
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2023-11-08 16:06:39 -08:00 |
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naichewa
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997318d7f9
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updated to-do comments
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2023-11-08 15:28:51 -08:00 |
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naichewa
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7d88050ecd
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fix hardware interlock, hold mode deassert
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2023-11-08 15:20:51 -08:00 |
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James E. Stine
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30c230ba95
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Update to ppaSynth and ppaAnalyze - still have to push in mod for ppaAnalyze to plot more refined plots as well as some other plots - I have a fix working - just need to push in which will do later today
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2023-11-08 14:00:36 -06:00 |
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James E. Stine
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825386241a
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add typo on setting WALLY for C-shell that caused some incompatability issues
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2023-11-08 13:59:04 -06:00 |
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Rose Thompson
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34d521a9ba
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Merge pull request #455 from davidharrishmc/dev
Bit manipulation imperas config, fsqrt code changes to match chapter
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2023-11-08 08:27:15 -08:00 |
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David Harris
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e7bb50c81e
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-08 02:55:00 -08:00 |
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David Harris
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f3e9c32fb4
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Merge pull request #456 from naichewa/main
fifo fixes and edge case testing
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2023-11-08 02:54:06 -08:00 |
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naichewa
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fbeaad4150
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fifo fixes and edge case testing
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2023-11-07 17:59:46 -08:00 |
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David Harris
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1bac0de954
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Reparitioned sign logic in fdivsqrt to match paper
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2023-11-06 14:11:42 -08:00 |
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