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updated to-do comments

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naichewa 2023-11-08 15:28:51 -08:00
parent 7d88050ecd
commit 997318d7f9
1 changed files with 1 additions and 2 deletions
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src/uncore/spi_apb.sv
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@ -27,7 +27,6 @@
// Current limitations: Flash read sequencer mode not implemented, dual and quad modes untestable with current test plan.
// HoldModeDeassert make sure still works
// Comment on FIFOs: watermark calculations
// Comment all interface and internal signals on the lines they are declared
// Get tabs correct so things line up
@ -36,7 +35,7 @@
/*
SPI module is written to the specifications described in FU540-C000-v1.0. At the top level, it is consists of synchronous 8 byte transmit and recieve FIFOs connected to shift registers.
The FIFOs are connected to WALLY by an apb bus control register interface, which includes various control registers for modifying the SPI transmission along with registers for writing
The FIFOs are connected to WALLY by an apb control register interface, which includes various control registers for modifying the SPI transmission along with registers for writing
to the transmit FIFO and reading from the receive FIFO. The transmissions themselves are then controlled by a finite state machine. The SPI module uses 4 tristate pins for SPI input/output,
along with a 4 bit Chip Select signal, a clock signal, and an interrupt signal to WALLY.
*/