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Author SHA1 Message Date
bbracker
3379b74bb2 intentionally breaking commit 2021-12-07 13:27:34 -08:00
bbracker
cf61187273 undo intentionally breaking commit 2021-12-07 13:27:06 -08:00
bbracker
69f025a642 intentionally breaking commit 2021-12-07 13:23:19 -08:00
bbracker
ec6c3bd74c 2nd attempt at making regression-wally.py able to be run from a different dir 2021-12-07 13:13:30 -08:00
bbracker
0c48725fa5 fix checkpointing so that it can find the synchronized reset signal 2021-12-07 13:12:06 -08:00
bbracker
9fc4f3bfef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-07 11:16:51 -08:00
bbracker
0692372037 attempt to make regression-wally.py more path-independent such that git bisect can invoke it directly 2021-12-07 11:16:43 -08:00
Ross Thompson
51e2b9ea6f Added information on how to copy the linux image to flash card. 2021-12-07 13:16:38 -06:00
bbracker
8e2a9d5bbb add buildroot tv linking to make-tests.sh 2021-12-07 11:15:59 -08:00
Ross Thompson
c7be8a701e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-07 13:12:59 -06:00
Ross Thompson
8bb3d51aad Added generate around the dtim preload. 
Added readme to explain FPGA.
 2021-12-07 13:12:47 -06:00
Ross Thompson
3d829dbbd3 Fixed two issues. 
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
 2021-12-07 12:15:50 -06:00
bbracker
ffe7cf83e5 regression.py bugfix 2021-12-06 19:32:38 -08:00
bbracker
b714490f92 add make-tests scripts 2021-12-06 15:37:33 -08:00
bbracker
d702599d56 add buildroot-only option to regression 2021-12-06 14:13:58 -08:00
bbracker
6c9db52801 linux-testvectors symlinks shouldn't be in repo, especially not in this location 2021-12-05 22:03:51 -08:00
Ross Thompson
517cae796c Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
David Harris
19fb0aace8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-04 20:26:01 -08:00
David Harris
83765ea3bc Added files to repo 2021-12-04 20:25:33 -08:00
Ross Thompson
e438592476 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-03 17:56:00 -06:00
Ross Thompson
41258529f0 Fixed bug in the top level of fpga verilog. 2021-12-03 17:55:36 -06:00
Ross Thompson
cb744280c3 Fixed a bunch of fpga issues. 2021-12-03 17:47:54 -06:00
Skylar Litz
a69ab3bd1b fix some interrupt timing bugs 2021-12-03 12:32:38 -08:00
Ross Thompson
35dd1b5c9f Improved FPGA makefile and fixed timing constraints in clock converter. 2021-12-03 10:05:13 -06:00
Ross Thompson
755c3e6a4c Fixed buildroot to work with the fpga's merge. 2021-12-02 18:09:43 -06:00
Ross Thompson
74ffb48c0a Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
Ross Thompson
b7e8c74e61 Merge branch 'fpga' into main 2021-12-02 14:28:10 -06:00
Ross Thompson
5d4051d1c2 Constraints for fpga are still wrong. 2021-12-02 14:23:21 -06:00
kwan
e4f214090d .* resolved in ifu.sv 2021-12-02 10:32:35 -08:00
kwan
2a77bc8053 .* in ifu/ifu.sv eliminated 2021-12-02 09:45:55 -08:00
Ross Thompson
2cfbdb1c47 Added tcl commands to build the implementation. 2021-12-02 10:17:30 -06:00
Ross Thompson
2a7467c76d Separated timing constraints from ILA. 2021-12-01 18:15:04 -06:00
Ross Thompson
6a228ade04 Got fpga synthesis running from scripts. 2021-12-01 16:59:04 -06:00
David Harris
2519d7705b Merged makefile changes 2021-12-01 10:39:26 -08:00
David Harris
6d936ee499 Makefile organization 2021-12-01 10:38:46 -08:00
Kevin Kim
c2274ce18e Makefile cleaning 2021-12-01 10:06:54 -08:00
David Harris
e4861e11d1 Added coremark scripts to regression directory 2021-12-01 09:08:06 -08:00
David Harris
40acc70e21 Updated Makefile 2021-12-01 09:06:33 -08:00
Kevin Kim
fcbbb3d198 Makefile up and running 2021-11-30 23:02:02 -08:00
Kevin Kim
fa73180ce4 changed readme to reflect submodule updates 2021-11-30 18:26:49 -08:00
Kevin Kim
869cd44533 added arch-test submodule 2021-11-30 18:22:08 -08:00
Kevin Kim
6323609da9 Added git submodules 
-riscv-arch-test
-rscv-isa-sim
submodules are added in addins/ directory
 2021-11-30 18:16:37 -08:00
Ross Thompson
96926877c4 Created top level FPGA module which replicates the schematic of the initial fpga design. 2021-11-30 17:18:28 -06:00
David Harris
273e211660 testing push 2021-11-30 11:20:09 -08:00
David Harris
2060140337 Coremark updates 2021-11-30 11:16:13 -08:00
Ross Thompson
7f52d86980 Added make clean to fpga IP generator. 2021-11-29 18:42:28 -06:00
Ross Thompson
1117b90f40 Created Makefile to manage IP generation. 2021-11-29 18:33:58 -06:00
Ross Thompson
84116a756e Added final IP generator script (proc_sys_reset). 2021-11-29 17:43:47 -06:00
Ross Thompson
d7df9c1054 Fixed uart for FPGA config after merge. This still needs some work. 2021-11-29 16:07:54 -06:00
Ross Thompson
ce91732856 Added ddr4 generator script. 2021-11-29 15:56:57 -06:00