David Harris
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32f8841f79
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Added MCONFIGPTR CSR hardwired to 0
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2022-05-12 04:31:45 +00:00 |
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David Harris
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bfb07f4572
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Added examples/asm/trap trap handler example
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2022-05-12 04:31:00 +00:00 |
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David Harris
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c738c130de
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merged ppa.sv
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2022-05-11 18:14:16 +00:00 |
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David Harris
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e37d262e4c
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PPA script progress
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2022-05-11 18:11:51 +00:00 |
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mmasserfrye
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70fe1184db
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ed
modified ppa.sv
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2022-05-11 16:22:12 +00:00 |
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mmasserfrye
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ff64dc4b1b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-11 16:16:23 +00:00 |
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mmasserfrye
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6aafe7b864
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modified ppa.sv to match module name and added madzscript
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2022-05-11 16:13:01 +00:00 |
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David Harris
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a8c9f504fa
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Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
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2022-05-11 15:08:33 +00:00 |
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David Harris
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91472eb948
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Removed M suffix from interrupts because they are generated asynchronously to pipeline
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2022-05-11 14:41:55 +00:00 |
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David Harris
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91b786c58d
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Updated PPA experiment
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2022-05-10 23:09:42 +00:00 |
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David Harris
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d53e4b1b1f
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Initial PPA study
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2022-05-10 20:48:47 +00:00 |
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David Harris
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b869190161
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endian swapper
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2022-05-08 06:51:50 +00:00 |
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David Harris
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8066ba45e8
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Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
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2022-05-08 06:46:35 +00:00 |
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David Harris
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2792d77e4e
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Fixed bug in delegated interrupts not being taken
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2022-05-08 04:50:27 +00:00 |
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David Harris
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2cdd49c7d2
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WFI terminates when an interrupt is pending even if interrupts are globally disabled
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2022-05-08 04:30:46 +00:00 |
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David Harris
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7024293a59
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Zero'd wfiM when ZICSR not supported to fix hang in E tests
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2022-05-05 15:32:13 +00:00 |
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David Harris
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66424a8246
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SFENCE.VMA should be illegal in user mode
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2022-05-05 15:15:02 +00:00 |
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David Harris
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866540580a
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SFENCE.VMA should be illegal in user mode
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2022-05-05 14:59:52 +00:00 |
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David Harris
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c100c9893b
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wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
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2022-05-05 14:37:21 +00:00 |
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David Harris
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94459ade3d
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Changed WFI to stall pipeline in memory stage
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2022-05-05 02:03:44 +00:00 |
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Kip Macsai-Goren
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8f748c4014
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clarified some trap causing functions to use zzero register rather than li [reg] 0x0. Also updated signatures' tvals
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2022-05-04 23:01:23 +00:00 |
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Kip Macsai-Goren
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88173b8bb3
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added explicit clears to mstatus.mie
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2022-05-04 23:00:17 +00:00 |
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Kip Macsai-Goren
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6a182efe0f
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Updated test libraries to reflect variable name changes
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2022-05-04 21:39:36 +00:00 |
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Kip Macsai-Goren
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6a372b1a1d
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renamed test_loop_setup to run_test_loop
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2022-05-04 21:39:09 +00:00 |
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Kip Macsai-Goren
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393edc9fd8
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renamed debug to extended signature
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2022-05-04 21:38:37 +00:00 |
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Kip Macsai-Goren
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25ad39939f
|
put privileged tests back into rv32/64gc
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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0f70e48b6b
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updated makefrag and tests.vh to reflect removed tests, new names
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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923cbc59a3
|
removed fp-diabled test and leftover mimpid test
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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3cab9f0234
|
removed instruction misaligned tests from trap tests, signatures
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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8c96672080
|
renamed all tests to have lower-case titles except for WALLY
|
2022-05-04 21:20:25 +00:00 |
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David Harris
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8eee0c0ca3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-03 18:32:04 +00:00 |
|
David Harris
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554c2b3550
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Illegal instruction fault when running FPU instruction with STATUS_FS = 0
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2022-05-03 18:32:01 +00:00 |
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David Harris
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cb1a7d54a4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-03 08:53:35 -07:00 |
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David Harris
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4fbf78e049
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clean up sram1p1rw; still doesn't work on Modelsim 2022.1
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2022-05-03 08:31:54 -07:00 |
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David Harris
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9c4de0e9c1
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FPU generates illegal instruction if MSTATUS.FS = 00
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2022-05-03 11:56:31 +00:00 |
|
David Harris
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dee32f70bf
|
Switched to behavioral comparator for best PPA
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2022-05-03 11:00:39 +00:00 |
|
David Harris
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bc123b5564
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Comparator experiments
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2022-05-03 10:54:30 +00:00 |
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David Harris
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7e3f75a35d
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Formatting cache.sv
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2022-05-03 10:53:20 +00:00 |
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David Harris
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bc132c3e20
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sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera
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2022-05-03 03:50:41 -07:00 |
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David Harris
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3f2ec0499f
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Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.
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2022-05-03 03:45:41 -07:00 |
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David Harris
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7268ff1fd4
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Changed loop variable in CLINT because of error only seen on VLSI
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2022-05-03 10:10:28 +00:00 |
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Kip Macsai-Goren
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208827502e
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general test cleanup of comments and old files
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2022-04-29 19:55:29 +00:00 |
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Kip Macsai-Goren
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7148429f4a
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re-renamed status-mie-s to status-sie
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2022-04-29 19:55:13 +00:00 |
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Kip Macsai-Goren
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e557e420b6
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added missing SIE test
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2022-04-29 19:54:29 +00:00 |
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Kip Macsai-Goren
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f50aa61994
|
renamed registers in test library to RISC-V ABI name rater than x2, etc..
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2022-04-29 18:52:42 +00:00 |
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Kip Macsai-Goren
|
5df381e26f
|
renamed PIE-stack tests to status-mie for clarity
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2022-04-29 18:30:39 +00:00 |
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Kip Macsai-Goren
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c3ffcd0e95
|
removed old unused tests from wally arch tests
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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562296c677
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added missing output for sret
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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3d1e1202f3
|
set WFI timeout to after 16 bits of counting for all configs
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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0e5cc40360
|
added 32 bit versions of new tests. all but timeout wait pass regression
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2022-04-28 18:14:07 +00:00 |
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