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139 Commits

Author SHA1 Message Date
dependabot[bot]
1025548a3a
Bump addins/cvw-arch-verif from 95f849e to efd70ce 
Bumps [addins/cvw-arch-verif](https://github.com/openhwgroup/cvw-arch-verif) from `95f849e` to `efd70ce`.
- [Commits](95f849e42e...efd70ce71a)

---
updated-dependencies:
- dependency-name: addins/cvw-arch-verif
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2024-12-16 14:02:24 +00:00
dependabot[bot]
421da19b8f
Bump addins/cvw-arch-verif from b37edba to 95f849e 
Bumps [addins/cvw-arch-verif](https://github.com/openhwgroup/cvw-arch-verif) from `b37edba` to `95f849e`.
- [Commits](b37edba7f6...95f849e42e)

---
updated-dependencies:
- dependency-name: addins/cvw-arch-verif
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2024-12-09 13:20:11 +00:00
dependabot[bot]
cfe15481e4
Bump addins/cvw-arch-verif from d6bae48 to b37edba 
Bumps [addins/cvw-arch-verif](https://github.com/openhwgroup/cvw-arch-verif) from `d6bae48` to `b37edba`.
- [Commits](d6bae481c7...b37edba7f6)

---
updated-dependencies:
- dependency-name: addins/cvw-arch-verif
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2024-12-02 14:23:25 +00:00
Jordan Carlin
daddbed8e6
Revert "Bump addins/verilog-ethernet from c180b22 to 6f5ea41" 2024-11-26 08:15:36 -08:00
Jordan Carlin
6b792f8760
Update cvw-arch-verif to version with isacov 2024-11-25 20:33:36 -08:00
Jordan Carlin
58628ed370
Remove riscvISACOV submodule 2024-11-25 15:43:11 -08:00
Jordan Carlin
486d1dbf33
Merge pull request #1131 from openhwgroup/dependabot/submodules/addins/vivado-boards-8ed4f99 
Bump addins/vivado-boards from `e5f0728` to `8ed4f99`
 2024-11-25 10:40:18 -08:00
Jordan Carlin
3c3f482a26
Merge pull request #1135 from openhwgroup/dependabot/submodules/addins/verilog-ethernet-6f5ea41 
Bump addins/verilog-ethernet from `c180b22` to `6f5ea41`
 2024-11-25 10:38:27 -08:00
dependabot[bot]
015b3f0d68
Bump addins/vivado-boards from e5f0728 to 8ed4f99 
Bumps [addins/vivado-boards](https://github.com/Digilent/vivado-boards) from `e5f0728` to `8ed4f99`.
- [Commits](e5f0728cd2...8ed4f9981d)

---
updated-dependencies:
- dependency-name: addins/vivado-boards
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2024-11-25 16:59:13 +00:00
Jordan Carlin
7d80a8992a
Remove FreeRTOS 2024-11-25 08:55:46 -08:00
dependabot[bot]
aa72ed1c19
Bump addins/verilog-ethernet from c180b22 to 6f5ea41 
Bumps [addins/verilog-ethernet](https://github.com/rosethompson/verilog-ethernet) from `c180b22` to `6f5ea41`.
- [Commits](c180b22ed5...6f5ea41584)

---
updated-dependencies:
- dependency-name: addins/verilog-ethernet
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2024-11-25 16:36:14 +00:00
Jordan Carlin
7be6311f51
Update cvw-arch-verif submodule 2024-11-25 08:11:50 -08:00
Jordan Carlin
2b57633217
Switch to out of tree riscv-arch-test with VM tests + add pmp & vm tests to testbench 2024-11-15 22:52:21 -08:00
Jordan Carlin
c926792941
Update riscv-arch-test 2024-11-15 20:24:03 -08:00
Jordan Carlin
c64c6c4cf1
Fix reverted submodules 2024-11-02 16:09:14 -07:00
naichewa
960d72295c Removed SPI hardware interlock test cases 2024-11-01 11:27:41 -07:00
Rose Thompson
d4fc3245b0 Removed ahbsdc submodule since it is no longer used. Updated old 
submodules pointing to ross144 to rosethompson repos.
 2024-10-15 10:11:12 -05:00
Mysterio-Abdullah
da35944dce Configuring Zcb 2024-10-13 17:41:59 -07:00
Jordan Carlin
1465a9f39f
Actually update riscv-arch-test 2024-09-23 22:08:11 -07:00
Jordan Carlin
2029cb9873
Update riscv-arch-test submodule 2024-09-23 15:22:40 -07:00
Jordan Carlin
cb944e0f92
Remove old testfloat and replace references 2024-09-15 01:03:03 -07:00
Jordan Carlin
76a4ac4b22
Switch to using testfloat submodule 2024-09-15 00:37:04 -07:00
Jordan Carlin
7e41961dd1
Remove old softfloat and replace references 2024-09-15 00:34:18 -07:00
Jordan Carlin
4fe33415d6
Add softfloat as submodule 2024-09-15 00:20:39 -07:00
David Harris
ae225b7a7a Updated cvw-arch-verif 2024-09-05 16:41:58 -07:00
Rose Thompson
65e338e762 Merges Jordan's wally.do updates with the new fcov2 changes. Updates 
cvw-arch-verif commit.
 2024-08-30 12:31:26 -07:00
Rose Thompson
a1c6bc854e Fixed a subtle questa sim bug with imperasDV. On some linux systems 
vsim will default to 32-bit mode rather than 64-bit, but the ImperasDV
libraries are 64-bit.  vsim must run in 64-bit mode.
 2024-08-29 14:00:52 -07:00
Rose Thompson
418bc6b23c Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-21 16:24:10 -07:00
Rose Thompson
f5d754d2a5 Updated to point to latest commit of cvw-arch-verif. 2024-08-21 11:02:23 -07:00
Huda-10xe
b315a8e338 Adding regression commands to Makefile 2024-08-21 15:45:23 +05:00
Huda-10xe
ca21b865b3 Adding regression commands to Makefile 2024-08-21 15:45:23 +05:00
Jordan Carlin
02f93655ba
Remove compiled softfloat binary 2024-08-15 19:01:13 -07:00
Jordan Carlin
1d3edc73be Remove compiled softfloat binary 2024-08-15 19:01:13 -07:00
David Harris
77b45f2d75 Fix creating cvw-arch-verif work directory 2024-08-08 05:25:28 -07:00
David Harris
c5c49d3cc0 Fix creating cvw-arch-verif work directory 2024-08-08 05:25:28 -07:00
Rose Thompson
27f89fcdbd Updated verilog-ethernet to remove all verilator warnings or at least suppress them. 2024-07-24 10:13:03 -05:00
Rose Thompson
fb1869fcb9 Updated verilog-ethernet to remove all verilator warnings or at least suppress them. 2024-07-24 10:13:03 -05:00
Rose Thompson
121342f4cc Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI. 2024-07-22 16:12:06 -05:00
Rose Thompson
3c06556833 Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI. 2024-07-22 16:12:06 -05:00
Rose Thompson
7223b15134 Merge branch 'rvvi' 2024-07-22 12:01:01 -05:00
Rose Thompson
02f108345a Merge branch 'rvvi' 2024-07-22 12:01:01 -05:00
Rose Thompson
0d40b8c933 Cleanup in prep to merge the rvvi branch into main. 2024-07-19 15:48:20 -05:00
Rose Thompson
ce2cc48642 Updated verilog-ethernet to be compatible with wally. 2024-07-19 13:36:26 -05:00
Rose Thompson
9c1779a2d5 Added some documenation about sparse-checkout for verilog-ethernet submodule. 2024-07-19 13:11:48 -05:00
Rose Thompson
79d0cb96c2 Added verilog-ethernet as a submodule. Hoping we can make use of sparse-checkout as there are so many files in this repo. 2024-07-18 18:22:26 -05:00
Jordan Carlin
569ccfd829
Update riscv-arch-test submodule 2024-06-18 23:34:02 -07:00
Jordan Carlin
f410bbb79e
Use Zfa tests from riscv-arch-test instead of wally-riscv-arch-test 2024-05-21 00:04:27 -07:00
Quswar Abid
f999ccadf4 /cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch 2024-04-26 15:55:39 -07:00
David Harris
3950588b8c Brought subrepos up to date 2024-04-24 07:36:42 -07:00
Quswar Abid
6f16b7e0c9 updated the submodules -> riscv-arch-tests and riscv-dv 2024-04-17 10:25:36 -07:00