mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 04:54:29 +00:00
aa72ed1c19
Bumps [addins/verilog-ethernet](https://github.com/rosethompson/verilog-ethernet) from `c180b22` to `6f5ea41`.
- [Commits](
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.. | ||
berkeley-softfloat-3@3b70b5d814 | ||
berkeley-testfloat-3@03c13d21db | ||
branch-predictor-simulator@3e424e902f | ||
coremark@f3e8f2e094 | ||
cvw-arch-verif@812f30af76 | ||
embench-iot@54fd9a0f10 | ||
FreeRTOS-Kernel@17a46c252f | ||
riscv-arch-test@a079bb263b | ||
riscv-dv@f0c570d112 | ||
riscvISACOV@ac9fa2d386 | ||
verilog-ethernet@6f5ea41584 | ||
vivado-boards@e5f0728cd2 | ||
README.md | ||
sparse-checkout |
verilog-ethernet contains many ethernet devices. Wally's synthesizable RVVI interface only requires a small subset of these files. To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info This will make the working directory only contain the necessary files.