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9c1779a2d5
cvw/addins
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Rose Thompson 9c1779a2d5 Added some documenation about sparse-checkout for verilog-ethernet submodule.
2024-07-19 13:11:48 -05:00
..
ahbsdc@33418c8dc1 Replaced the git@github with hptts:github submodule for ahbsdc which I hope will fix Lee's clone issue 2023-12-11 14:12:38 -06:00
branch-predictor-simulator@3e424e902f Swap in branch predictor simulator handling compressed instruction offsets 2023-11-21 16:42:41 -08:00
coremark@f3e8f2e094
embench-iot@54fd9a0f10
FreeRTOS-Kernel@17a46c252f
riscv-arch-test@1498e95cc6 Brought subrepos up to date 2024-04-24 07:36:42 -07:00
riscv-dv@f0c570d112 /cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch 2024-04-26 15:55:39 -07:00
SoftFloat-3e
TestFloat-3e
verilog-ethernet@baac5f8d81 Added verilog-ethernet as a submodule. Hoping we can make use of sparse-checkout as there are so many files in this repo. 2024-07-18 18:22:26 -05:00
vivado-boards@e5f0728cd2
README.md Added some documenation about sparse-checkout for verilog-ethernet submodule. 2024-07-19 13:11:48 -05:00
sparse-checkout Added some documenation about sparse-checkout for verilog-ethernet submodule. 2024-07-19 13:11:48 -05:00

README.md

verilog-ethernet contains many ethernet devices. Wally's synthesizable RVVI interface only requires a small subset of these files. To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info This will make the working directory only contain the necessary files.