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Author SHA1 Message Date
Ross Thompson
626a918668 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
25103176a0 Updated fpga wave config. 2023-06-19 12:28:30 -05:00
Ross Thompson
8242544efa Updated fpga wally wrapper to work with the ILA. 2023-06-19 12:15:48 -05:00
Ross Thompson
1d2eb60ffb Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-18 16:37:19 -05:00
Ross Thompson
faf09a89c2
Merge pull request #344 from davidharrishmc/dev 
Embench and coverage fixes
 2023-06-18 17:36:37 -04:00
David Harris
60931e7d5c Fixed embench to run all tests, even ones not in 1.0 2023-06-17 20:38:51 -07:00
harshinisrinath
dc6633c796 Improved testing of pmd in priv. 2023-06-16 17:13:54 -07:00
David Harris
7bea99aabb
Merge pull request #343 from harshinisrinath1001/main 
Improve test coverage on ieu fw.
 2023-06-16 16:11:51 -07:00
harshinisrinath
c9695e6813 Improve test coverage on ieu fw. 2023-06-16 16:09:48 -07:00
David Harris
e2f927b4e6 Replaced zext.h with zext.h_64 in rv64 tests because old one is obsolete 2023-06-16 16:07:28 -07:00
David Harris
95960620a2 Removed redundant and not-covered atomic check from StoreStallD 2023-06-16 16:05:53 -07:00
Ross Thompson
24b8c6c391 I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug. 2023-06-16 17:00:27 -05:00
Ross Thompson
4bee446cad Vivado requires an intermediate wrapper file for parameterization. 2023-06-16 16:30:14 -05:00
Ross Thompson
2f35bec970 FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. 2023-06-16 15:40:13 -05:00
David Harris
dfedc13cfc erge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:32:37 -07:00
David Harris
281c036e70
Merge pull request #342 from ross144/main 
Testbench generates embench output files
 2023-06-16 10:32:18 -07:00
Ross Thompson
509aee36ef Modified the testbench to generate the required files for embench scripts. 2023-06-16 12:27:22 -05:00
David Harris
2d94800ad7 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:03:48 -07:00
David Harris
1cb0cf38b4
Merge pull request #341 from ross144/main 
Fix embench so it does not crash
 2023-06-16 10:03:41 -07:00
Ross Thompson
3f628d6bf2 embench testbench no longer crashes. 2023-06-16 11:54:41 -05:00
David Harris
3c98ed9e29 Added assertions for ZICNTR and ZIHPM 2023-06-16 09:26:02 -07:00
David Harris
557e991376
Merge pull request #340 from eroom1966/main 
Incorporate changes for IDV
 2023-06-16 09:04:55 -07:00
David Harris
a5b6c5b96d
Merge pull request #339 from ross144/main 
Fixed imperas testbench to work with parameters
 2023-06-16 09:04:39 -07:00
eroom1966
9125f25880 add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
Lee Moore
98d2ab8160
Merge pull request #4 from ross144/main 
PR from Ross
 2023-06-16 15:24:07 +01:00
Ross Thompson
c26845e9ec Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-16 08:59:59 -05:00
Ross Thompson
605ddf7990 Fixed the imperas testbench to work with parameters. 2023-06-16 08:59:52 -05:00
David Harris
cfecd48752
Merge pull request #338 from ross144/main 
First pass at testbench restructuring
 2023-06-15 14:36:28 -07:00
Ross Thompson
110a41c046 Have the linux testbench working in the mean time. Before the consolidation. 2023-06-15 16:18:37 -05:00
Ross Thompson
6d31936e89 Added comment to uart LCR to check reset value after updating FPGA. 2023-06-15 15:39:51 -05:00
Ross Thompson
34d1d50b87 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
a011b7d591 Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
7278e0b2cc
Merge pull request #333 from davidharrishmc/dev 
cvw.sv moved to root to avoid warnings; UART cleanup and QEMU removal
 2023-06-15 16:28:21 -04:00
Ross Thompson
a55bcad5c1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
Ross Thompson
3c4677ef63 Major cleanup of testbench. 2023-06-15 14:57:05 -05:00
David Harris
52ab586a9d Added input gating on FPU 2023-06-15 12:38:33 -07:00
David Harris
524d8e8469 Gated MDU to save power; doesn't seem to have affected simulation time 2023-06-15 12:17:23 -07:00
David Harris
c7d06382b3 Bit manipulation comment cleanup 2023-06-15 12:16:46 -07:00
Ross Thompson
e3cf1419ed Deleted remaining old configs except fpga as I still need to create the parameterized version. 2023-06-15 14:08:13 -05:00
Ross Thompson
44c72c20e2 Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
David Harris
33ff9766b4 Gated inputs to BMU when inactive to save power and simulation time 2023-06-15 11:56:59 -07:00
Ross Thompson
2fc8080102 Got the srams parameterized correctly now. 2023-06-15 13:42:24 -05:00
David Harris
e0b6a2d693 Fixed UART merge conflict 2023-06-15 11:36:37 -07:00
David Harris
cdee4e9b91
Merge pull request #337 from harshinisrinath1001/main 
Fixed the spacing of the uncore and wally modules
 2023-06-15 11:33:29 -07:00
Ross Thompson
e431f90cf3 Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Harshini Srinath
37c930bb27
Update wallypipelinedsoc.sv 
Program clean up
 2023-06-15 10:39:37 -07:00
Harshini Srinath
fd00067b7f
Update wallypipelinedcore.sv 
Program clean up
 2023-06-15 10:38:38 -07:00
Harshini Srinath
e3f8280ff9
Update cvw.sv 
Program clean up
 2023-06-15 10:29:33 -07:00
Harshini Srinath
e9cfbd95f4
Update uncore.sv 
Program clean up
 2023-06-15 10:23:47 -07:00
Harshini Srinath
5d8e120031
Update uart_apb.sv 
Program clean up
 2023-06-15 10:21:46 -07:00