Ross Thompson
6a82ee0579
Fixed debug2.xdc to match wally changes.
2022-02-08 15:23:44 -06:00
Ross Thompson
b621eb78fb
Updated debug2 ila signal names.
2022-01-28 11:43:49 -06:00
Ross Thompson
1bb8d36308
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
728e46a794
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
Ross Thompson
db197b6491
Added pin location for reset on VCU118 board. Somehow this was missing and still worked.
2022-01-25 17:48:42 -06:00
Ross Thompson
71eb1df492
Added comport.setup to remind how to configure com port for xilinx fpga.
...
Added load-deadlock.tsm to trigger load operation deadlock.
2022-01-25 14:54:38 -06:00
David Harris
ca1f7ce5d3
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
Ross Thompson
05ebadacad
Added PCNextF and PostSpillInstrRawF to ila.
2022-01-19 14:05:14 -06:00
Ross Thompson
305fccfe7a
Fixed fpga ila debug to match lsu changes.
2022-01-18 21:13:18 -06:00
Ross Thompson
5cf686429d
Merged in the debug ila updates.
2022-01-18 17:29:21 -06:00
David Harris
f7f3882cb8
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
d9e8d16bbe
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
Ross Thompson
26fb09c868
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
6eb2f37ce4
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
09d605ac6a
Updated debug constraints again to match changes in verilog.
2022-01-08 13:28:51 -06:00
Ross Thompson
88d5edaf13
Added advanced Vivado debug scripts.
2022-01-07 17:56:40 -06:00
Ross Thompson
3625fc3bed
Patched the ILA's debug2.xdc constraint file to work with the wally memory design.
2022-01-06 15:18:18 -06:00
Ross Thompson
c19b910f6e
Updated fpga ILA constraints to match the new changes to the rtl.
2022-01-06 11:56:09 -06:00
Ross Thompson
1ab3a17ff7
Updates to support fpga.
2022-01-05 18:07:23 -06:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
Ross Thompson
53736096a6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
0257c08641
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
79ec4161b6
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
9f798250ea
Oups missed files in the last commit.
2021-12-15 10:25:08 -06:00
Ross Thompson
54767822ec
Reverted 23Mhz to 10Mhz. The flash card can't work at that speed.
...
added icache debugging signals.
2021-12-15 10:24:29 -06:00
Ross Thompson
f061a26411
Cleaned up fpga synthesis script.
2021-12-13 18:26:54 -06:00
Ross Thompson
bb79f70a63
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
2021-12-12 17:21:44 -06:00
Ross Thompson
e6f2a316c8
Missed constraints file for xilinx ILA.
2021-12-12 15:06:29 -06:00
Ross Thompson
51e2b9ea6f
Added information on how to copy the linux image to flash card.
2021-12-07 13:16:38 -06:00
Ross Thompson
8bb3d51aad
Added generate around the dtim preload.
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Added readme to explain FPGA.
2021-12-07 13:12:47 -06:00
Ross Thompson
3d829dbbd3
Fixed two issues.
...
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
Ross Thompson
517cae796c
Fixed more constraint issues in fpga.
...
Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
Ross Thompson
41258529f0
Fixed bug in the top level of fpga verilog.
2021-12-03 17:55:36 -06:00
Ross Thompson
cb744280c3
Fixed a bunch of fpga issues.
2021-12-03 17:47:54 -06:00
Ross Thompson
35dd1b5c9f
Improved FPGA makefile and fixed timing constraints in clock converter.
2021-12-03 10:05:13 -06:00
Ross Thompson
5d4051d1c2
Constraints for fpga are still wrong.
2021-12-02 14:23:21 -06:00
Ross Thompson
2cfbdb1c47
Added tcl commands to build the implementation.
2021-12-02 10:17:30 -06:00
Ross Thompson
2a7467c76d
Separated timing constraints from ILA.
2021-12-01 18:15:04 -06:00
Ross Thompson
6a228ade04
Got fpga synthesis running from scripts.
2021-12-01 16:59:04 -06:00
Ross Thompson
96926877c4
Created top level FPGA module which replicates the schematic of the initial fpga design.
2021-11-30 17:18:28 -06:00
Ross Thompson
7f52d86980
Added make clean to fpga IP generator.
2021-11-29 18:42:28 -06:00
Ross Thompson
1117b90f40
Created Makefile to manage IP generation.
2021-11-29 18:33:58 -06:00
Ross Thompson
84116a756e
Added final IP generator script (proc_sys_reset).
2021-11-29 17:43:47 -06:00
Ross Thompson
ce91732856
Added ddr4 generator script.
2021-11-29 15:56:57 -06:00
Ross Thompson
9a0bf54840
Created tcl scripts to build 2 of the 4 xilinx IP.
2021-11-29 11:26:08 -06:00
Ross Thompson
2e0dcaaff9
Fpga simualtion files.
2021-10-11 10:24:40 -05:00
