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2f85ac7f38
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Author SHA1 Message Date
Ross Thompson
2f85ac7f38 Fixed a very complex interaction between interrupts, the icache, dcache, and hptw. 
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
 2021-11-20 22:35:47 -06:00
slmnemo
870549c01a Removed .* from hazard hzu(.*). 2021-11-17 14:21:23 -08:00
slmnemo
a98dcd11ee Removed .* from hazard hzu(.*) in wallypipelinedhart.sv. 2021-11-17 14:08:08 -08:00
slmnemo
fed613dc72 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:38:51 -08:00
slmnemo
f4380faa4e removed .* from muldiv.sv (REAL) 2021-11-17 13:37:50 -08:00
Noah Limpert
0ccc7d5fe8 ieu variable naming changed for clarity 2021-11-17 13:24:28 -08:00
slmnemo
9fb26d5a61 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:23:20 -08:00
slmnemo
573f8b0c42 Removed .*s from muldiv.sv 2021-11-17 13:23:12 -08:00
Noah Limpert
ed2285b8e7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:04:33 -08:00
Noah Limpert
832b23b8a4 Updated IFU variable naming for clarity 2021-11-17 12:39:05 -08:00
Kevin Kim
d4e9376854 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 12:18:25 -08:00
Kevin Kim
34b3cc1c8d root level makefile added 2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
3f76549a7d renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv 2021-11-17 10:53:17 -08:00
slmnemo
39983ab2c6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 10:39:52 -08:00
slmnemo
3b4c14e048 Removed .* from muldiv. 2021-11-17 10:39:18 -08:00
Skylar Litz
e35faa9b8a fixed interrupt timing bug 2021-11-16 16:46:17 -08:00
davidharrishmc
984a7a6ccd Update README.md 
updated linux_testvectors path
 2021-11-16 12:33:47 -08:00
bbracker
23bd24323b get current privilege level from GDB for checkpoints 2021-11-15 14:49:00 -08:00
Skylar Litz
99a15e7897 fix timing of delayed interrupt 2021-11-11 09:35:51 -08:00
kipmacsaigoren
e90d0eee72 fixed small errors causing overwrites in timing reports 2021-11-10 13:01:09 -06:00
Kevin Kim
a7684f1b59 Makefile added in regression directory: 
-cd's into imperas then runs make commands, finally running the tvLinker script
 2021-11-09 10:55:48 -08:00
bbracker
24c5796680 genCheckpoint path bugfix 2021-11-06 15:25:10 -07:00
bbracker
b3288beb38 update README.md to reflect new tvLinker location 2021-11-06 15:02:16 -07:00
bbracker
1597e0dac6 increase expectations for buildroot and timeout count 2021-11-06 14:57:29 -07:00
bbracker
e585a173e5 automated checkpoint generator 2021-11-06 14:37:49 -07:00
bbracker
d0ad8d3ae3 update tvLinker to new shared dir 2021-11-06 14:15:16 -07:00
bbracker
31d38286da make genCheckpoint accept instr count as argument 2021-11-06 14:14:15 -07:00
bbracker
24d3244cfe checkpoint MIDELEG support 2021-11-06 03:44:23 -07:00
bbracker
1d3d7cbe1e fix merge conflict 2021-11-05 23:42:15 -07:00
bbracker
3077769cbd checkpoints now use binary ram files 2021-11-05 22:37:05 -07:00
kipmacsaigoren
e7b25f7c95 changed number of critical paths reported to 1, added lots of internal signals and new report files. 2021-11-05 11:59:33 -05:00
davidharrishmc
f540bb13c0 fixed 64i 2021-11-03 13:49:07 -07:00
davidharrishmc
099c4e8b6b fixed 64i 2021-11-03 13:40:23 -07:00
davidharrishmc
d957d86f3b added wally-riscv-arch-test compile commands 2021-11-03 13:30:21 -07:00
Kevin
b34569c358 changed code aligner to run recursively on a root directory 
-only runs the aligner on .sv files
-runs recursively on sub-directories
 2021-11-03 10:49:34 -07:00
slmnemo
5fc12d4ae9 edited to include missing instructions 
added cd tests before cd imperas-riscv-tests to reflect new tests folder
modified cd ../addins so we can point to it from the new imperas-riscv-tests within the tests folder
added instructions so the buildroot test exists
 2021-11-03 01:50:00 -07:00
slmnemo
ec214e4bf0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-03 00:50:27 -07:00
bbracker
e4cf044932 fix testbench interrupt timing 2021-11-02 21:19:12 -07:00
bbracker
730c52da23 genCheckpoint syntax fix 2021-11-01 15:31:38 -07:00
bbracker
8563c0f016 linux testgen refactor 2021-11-01 14:09:49 -07:00
David Harris
db268471b6 added some missing files 2021-11-01 13:36:07 -07:00
David Harris
0c829dd62c simplified header and footer 2021-11-01 13:24:18 -07:00
David Harris
910957704b Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
4b57af9cff PIPELINE test running 2021-11-01 12:44:35 -07:00
David Harris
c306884e2c Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
bbracker
38d26e857b fix buildroot graphical sim 2021-10-31 18:33:43 -07:00
davidharrishmc
e29c577627 Added instructions for rv64i_m/D 2021-10-30 07:34:53 -07:00
David Harris
e9244e7a85 Fixed exe2memfile parsing of weird line in arch64d test 2021-10-30 07:26:18 -07:00
David Harris
f35b31f166 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-29 22:32:08 -07:00
David Harris
717f9d48e9 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00