David Harris
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72c1cc33f5
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Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
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2021-09-15 13:14:00 -04:00 |
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Ross Thompson
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4549a9f1c9
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Merge branch 'main' into dcache
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2021-07-15 11:55:20 -05:00 |
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Ross Thompson
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ee09fa5f58
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Moved StoreStall into the hazard unit instead of in the d cache.
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2021-07-13 13:20:50 -05:00 |
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David Harris
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516b710db6
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Fixed busybear by restoring InstrValidW needed by testbench
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2021-07-13 14:17:36 -04:00 |
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Ross Thompson
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2004b2e044
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Fixed back to back store issue.
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
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2021-07-13 12:46:20 -05:00 |
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David Harris
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68d1f87101
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Fixed InstrValid from W to M stage for CSR performance counters
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2021-07-13 13:19:13 -04:00 |
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bbracker
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4e09793a9a
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ah merge; I checked and this does pass all of regression except lints
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2021-06-25 07:37:06 -04:00 |
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bbracker
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aac9b46a1f
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changed SC M-to-E fowarding to W-to-E forwarding to improve critical path
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2021-06-25 07:18:38 -04:00 |
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Katherine Parry
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bc8d660bc5
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FPU forwarding reworked pt.1
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2021-06-24 18:39:18 -04:00 |
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bbracker
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ced5039776
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Revert "fixed forwarding"
This reverts commit 0f4a4a6ade.
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2021-06-24 17:39:37 -04:00 |
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bbracker
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0f4a4a6ade
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fixed forwarding
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2021-06-24 11:20:21 -04:00 |
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David Harris
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9dd3857c26
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Fixed lint WIDTH errors
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2021-06-09 20:58:20 -04:00 |
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bbracker
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28abd28b1f
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fixed InstrValid signals and implemented less costly MEPC loading
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2021-06-02 10:03:19 -04:00 |
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Katherine Parry
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71e4a10efb
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FMV.D.X imperas test passes
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2021-05-20 22:17:59 -04:00 |
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Shreya Sanghai
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f35d3b39c8
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removed unnecesary PC registers in ifu
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2021-03-18 16:31:21 -04:00 |
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David Harris
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d4e84c58ed
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64-bit AMO debugged
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2021-03-11 23:18:33 -05:00 |
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David Harris
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fe4d288589
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Initial untested implementation of AMO instructions
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2021-03-11 00:11:31 -05:00 |
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David Harris
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bea8ac6d59
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WALLY-LRSC atomic test passing
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2021-03-09 09:28:25 -05:00 |
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Ross Thompson
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619bbd9d83
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Merge branch 'bp' into main
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
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2021-03-04 13:35:46 -06:00 |
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David Harris
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6f4e8b723e
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Initial (untested) implementation of lr and sc
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2021-03-01 00:09:45 -05:00 |
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Ross Thompson
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6191fcb1af
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Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
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2021-02-26 20:12:27 -06:00 |
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David Harris
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73920282af
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Eliminated flushing pipeline on CSR reads
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2021-02-26 17:00:07 -05:00 |
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David Harris
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0258901865
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Cleaned out unused signals
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2021-02-26 09:17:36 -05:00 |
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David Harris
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f57096a5d2
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Restored to working multiplier after Lab 2
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2021-02-25 15:32:43 -05:00 |
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David Harris
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cd4ba8831c
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Merged bus into main
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2021-02-25 00:28:41 -05:00 |
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David Harris
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492ec0ee78
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Removed multiplier for lab 2
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2021-02-17 16:06:16 -05:00 |
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David Harris
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a7dd20b388
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Multiply instructions working
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2021-02-17 15:29:20 -05:00 |
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David Harris
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adc5d5bc1a
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Added MUL
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2021-02-15 22:27:35 -05:00 |
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David Harris
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33110ed636
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Data memory bus integration
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2021-02-07 23:21:55 -05:00 |
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David Harris
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bb83fda1d8
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Moved writeback pipeline registers from datapth into DMEM and CSR
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2021-02-02 13:02:31 -05:00 |
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David Harris
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92bf1674b4
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Moved fpu to temporary location to fix compile and cleaned up interface formatting
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2021-02-01 23:44:41 -05:00 |
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David Harris
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07af481b67
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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