Jordan Carlin
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1465a9f39f
|
Actually update riscv-arch-test
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2024-09-23 22:08:11 -07:00 |
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Jordan Carlin
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2029cb9873
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Update riscv-arch-test submodule
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2024-09-23 15:22:40 -07:00 |
|
Jordan Carlin
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cb944e0f92
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Remove old testfloat and replace references
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2024-09-15 01:03:03 -07:00 |
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Jordan Carlin
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76a4ac4b22
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Switch to using testfloat submodule
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2024-09-15 00:37:04 -07:00 |
|
Jordan Carlin
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7e41961dd1
|
Remove old softfloat and replace references
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2024-09-15 00:34:18 -07:00 |
|
Jordan Carlin
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4fe33415d6
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Add softfloat as submodule
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2024-09-15 00:20:39 -07:00 |
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David Harris
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ae225b7a7a
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Updated cvw-arch-verif
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2024-09-05 16:41:58 -07:00 |
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Rose Thompson
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65e338e762
|
Merges Jordan's wally.do updates with the new fcov2 changes. Updates
cvw-arch-verif commit.
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2024-08-30 12:31:26 -07:00 |
|
Rose Thompson
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a1c6bc854e
|
Fixed a subtle questa sim bug with imperasDV. On some linux systems
vsim will default to 32-bit mode rather than 64-bit, but the ImperasDV
libraries are 64-bit. vsim must run in 64-bit mode.
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2024-08-29 14:00:52 -07:00 |
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Rose Thompson
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418bc6b23c
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-21 16:24:10 -07:00 |
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Rose Thompson
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f5d754d2a5
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Updated to point to latest commit of cvw-arch-verif.
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2024-08-21 11:02:23 -07:00 |
|
Huda-10xe
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b315a8e338
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Adding regression commands to Makefile
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2024-08-21 15:45:23 +05:00 |
|
Huda-10xe
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ca21b865b3
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Adding regression commands to Makefile
|
2024-08-21 15:45:23 +05:00 |
|
Jordan Carlin
|
02f93655ba
|
Remove compiled softfloat binary
|
2024-08-15 19:01:13 -07:00 |
|
Jordan Carlin
|
1d3edc73be
|
Remove compiled softfloat binary
|
2024-08-15 19:01:13 -07:00 |
|
David Harris
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77b45f2d75
|
Fix creating cvw-arch-verif work directory
|
2024-08-08 05:25:28 -07:00 |
|
David Harris
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c5c49d3cc0
|
Fix creating cvw-arch-verif work directory
|
2024-08-08 05:25:28 -07:00 |
|
Rose Thompson
|
27f89fcdbd
|
Updated verilog-ethernet to remove all verilator warnings or at least suppress them.
|
2024-07-24 10:13:03 -05:00 |
|
Rose Thompson
|
fb1869fcb9
|
Updated verilog-ethernet to remove all verilator warnings or at least suppress them.
|
2024-07-24 10:13:03 -05:00 |
|
Rose Thompson
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121342f4cc
|
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
|
2024-07-22 16:12:06 -05:00 |
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Rose Thompson
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3c06556833
|
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
|
2024-07-22 16:12:06 -05:00 |
|
Rose Thompson
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7223b15134
|
Merge branch 'rvvi'
|
2024-07-22 12:01:01 -05:00 |
|
Rose Thompson
|
02f108345a
|
Merge branch 'rvvi'
|
2024-07-22 12:01:01 -05:00 |
|
Rose Thompson
|
0d40b8c933
|
Cleanup in prep to merge the rvvi branch into main.
|
2024-07-19 15:48:20 -05:00 |
|
Rose Thompson
|
ce2cc48642
|
Updated verilog-ethernet to be compatible with wally.
|
2024-07-19 13:36:26 -05:00 |
|
Rose Thompson
|
9c1779a2d5
|
Added some documenation about sparse-checkout for verilog-ethernet submodule.
|
2024-07-19 13:11:48 -05:00 |
|
Rose Thompson
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79d0cb96c2
|
Added verilog-ethernet as a submodule. Hoping we can make use of sparse-checkout as there are so many files in this repo.
|
2024-07-18 18:22:26 -05:00 |
|
Jordan Carlin
|
569ccfd829
|
Update riscv-arch-test submodule
|
2024-06-18 23:34:02 -07:00 |
|
Jordan Carlin
|
f410bbb79e
|
Use Zfa tests from riscv-arch-test instead of wally-riscv-arch-test
|
2024-05-21 00:04:27 -07:00 |
|
Quswar Abid
|
f999ccadf4
|
/cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch
|
2024-04-26 15:55:39 -07:00 |
|
David Harris
|
3950588b8c
|
Brought subrepos up to date
|
2024-04-24 07:36:42 -07:00 |
|
Quswar Abid
|
6f16b7e0c9
|
updated the submodules -> riscv-arch-tests and riscv-dv
|
2024-04-17 10:25:36 -07:00 |
|
David Harris
|
fec160d6f9
|
Updated coremark to use wsim
|
2024-04-06 21:38:44 -07:00 |
|
Rose Thompson
|
6110799a1e
|
Updated the wally rv32 priv tests to not use sail.
|
2024-02-16 11:39:06 -06:00 |
|
David Harris
|
430d495ce5
|
Updated to latest riscv-arch-test
|
2023-12-31 10:04:20 -08:00 |
|
Rose Thompson
|
e38b43ae73
|
Replaced the git@github with hptts:github submodule for ahbsdc which I hope will fix Lee's clone issue
|
2023-12-11 14:12:38 -06:00 |
|
David Harris
|
d8186b9f58
|
Swap in branch predictor simulator handling compressed instruction offsets
|
2023-11-21 16:42:41 -08:00 |
|
David Harris
|
93a0db1fca
|
swapped branch predictor simulator
|
2023-11-21 15:02:09 -08:00 |
|
David Harris
|
2b2016271a
|
repo cleanup and start to add CMO tests
|
2023-11-20 23:41:36 -08:00 |
|
David Harris
|
8cb433cb66
|
Commented IROM preloading
|
2023-11-19 19:33:57 -08:00 |
|
Jacob Pease
|
a1e7158bd9
|
Merge branch 'main' of github.com:openhwgroup/cvw
|
2023-11-18 19:20:48 -06:00 |
|
Jacob Pease
|
38cf7f0fb7
|
ahbsdc submodule actually added this time.
|
2023-11-16 17:46:48 -06:00 |
|
Jacob Pease
|
9df87872ef
|
Deleted vivado-risc-v directory and added ahbsdc.
|
2023-11-16 15:13:12 -06:00 |
|
David Harris
|
7b2bb86ced
|
changed to head of riscv-arch-test
|
2023-11-15 09:48:13 -08:00 |
|
David Harris
|
90cf128349
|
Added back riscv-arch-test fresh
|
2023-11-15 05:48:33 -08:00 |
|
David Harris
|
18c29dd7d0
|
Removed riscv-arch-test submodule that appears corrupted
|
2023-11-15 05:46:38 -08:00 |
|
David Harris
|
8ba0336c6f
|
Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e
|
2023-11-14 11:01:58 -08:00 |
|
naichewa
|
75f1c07022
|
merge main, pull /A/ tests
|
2023-11-03 13:16:19 -07:00 |
|
Ross Thompson
|
b1f7a5768f
|
Removed all old references to the old flash card controller.
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
|
2023-07-24 15:45:57 -05:00 |
|
Ross Thompson
|
026570d3da
|
Added new submodule for digilent fpga boards.
|
2023-07-17 16:25:37 -05:00 |
|