Ross Thompson
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2f582cd91f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-30 13:30:37 -06:00 |
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Ross Thompson
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cedb234013
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Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
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2022-11-30 11:01:25 -06:00 |
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Ross Thompson
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0454eb95ad
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Preparing to merge dirty and tag srams.
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2022-11-30 10:40:48 -06:00 |
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Ross Thompson
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de538d1c2f
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Intermediate commit. Replaced flip flop dirty bit array with sram.
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2022-11-30 00:08:31 -06:00 |
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cturek
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10c2d45888
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div tests in sim-wally
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2022-11-30 02:32:04 +00:00 |
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Kip Macsai-Goren
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44ea8d8b22
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added failing satp invalid tests to regression
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2022-11-29 10:43:38 -08:00 |
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cturek
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78c2ce5649
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Updated testbench/wave for fdivsqrt new start signals
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2022-11-22 22:22:26 +00:00 |
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cturek
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9d30a832c3
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Reoredered tests for arch32m
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2022-11-09 18:42:00 +00:00 |
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cturek
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2cbe2fd70b
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Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
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2022-11-06 22:08:18 +00:00 |
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David Harris
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53a88fec8f
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Reorder embench tests to prevent crash
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2022-11-04 15:21:51 -07:00 |
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Ross Thompson
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a59df0c77d
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Created one off test to replicate the floating point forwarding hazard bug.
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2022-10-22 16:29:12 -05:00 |
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Kip Macsai-Goren
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c18c181fc0
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fixed endianness mstatush problem, passes make, not regression
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2022-10-04 17:37:39 +00:00 |
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David Harris
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e49e99548a
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Fixed testbench-fp to support all again
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2022-09-21 13:19:48 -07:00 |
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David Harris
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030fb79a3c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 10:35:11 -07:00 |
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David Harris
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cb4c3ff1ce
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Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest
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2022-09-21 10:35:08 -07:00 |
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Ross Thompson
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ac864a6ca3
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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David Harris
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87cde2c427
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make QmM size b+1 indpenedent of radix
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2022-09-20 03:25:09 -07:00 |
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David Harris
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8e90862dad
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Removed EarlyTermShift from fdiv
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2022-09-19 08:44:23 -07:00 |
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David Harris
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498c053aab
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FP testbench
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2022-09-18 21:27:21 -07:00 |
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David Harris
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f38bb5b32e
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Divide testfloat starts with half-precision tests
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2022-09-18 06:46:47 -07:00 |
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Kip Macsai-Goren
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cc7d1c8ef9
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Created initial endianness tests
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2022-09-16 01:06:26 +00:00 |
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Ross Thompson
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c7d3580637
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Renamed signals in the LSU.
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2022-09-13 11:47:39 -05:00 |
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David Harris
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c730ddf74a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-07 11:11:39 -07:00 |
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David Harris
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7a29f9c95b
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Running 16-bit square root cases first in testfloat
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2022-09-07 11:11:35 -07:00 |
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Ross Thompson
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0615798467
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-07 12:26:50 -05:00 |
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David Harris
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ce6e153b15
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Run 16-bit fsqrt tests first
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2022-09-07 10:26:09 -07:00 |
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Ross Thompson
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3571fb18c2
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Modified regression tests to add some ahb configurations.
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2022-09-07 12:03:58 -05:00 |
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DTowersM
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48a1abf06f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-31 00:18:04 +00:00 |
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DTowersM
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bdeb5c6509
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fixed qrduino keyerror in embench test
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2022-08-31 00:17:58 +00:00 |
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David Harris
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e1760dde55
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Fixed checking termination in testfloat testbench
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2022-08-30 10:55:21 -07:00 |
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David Harris
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2788022c22
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renamed srt to fdivsqrt
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2022-08-29 04:04:05 -07:00 |
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David Harris
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03e731b3ff
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Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
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2022-08-26 21:05:20 -07:00 |
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David Harris
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812158aeee
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Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
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2022-08-26 20:26:12 -07:00 |
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David Harris
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95dd50a567
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Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
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2022-08-26 20:12:03 -07:00 |
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Ross Thompson
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db635e3ad2
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 16:01:02 -05:00 |
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David Harris
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302a7fa294
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Extended HADDR to PA_BITS
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2022-08-25 13:11:36 -07:00 |
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Ross Thompson
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179aec3616
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Still not working with rv32ic.
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2022-08-25 15:03:54 -05:00 |
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Ross Thompson
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3b612d6201
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Possible fixes for earily messup of rv32ic and rv64ic configs.
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2022-08-25 14:42:08 -05:00 |
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Ross Thompson
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e605ef57dc
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BROKEN. Don't use this commit.
Issue running cacheless with bus.
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2022-08-25 11:02:46 -05:00 |
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Ross Thompson
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b0aea77b20
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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David Harris
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f7209627c2
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removed simpleram and modified dtim to use bram1p1rw
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2022-08-25 03:39:57 -07:00 |
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David Harris
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562be633ab
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Stripped write capaibilty out of rom_ahb
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2022-08-24 17:23:08 -07:00 |
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Ross Thompson
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769af32f2a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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fc22e807e2
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Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
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2022-08-24 17:52:25 -05:00 |
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Ross Thompson
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4a371b6829
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added SD card and external ram to common testbench.
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2022-08-24 13:27:18 -05:00 |
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Ross Thompson
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51adf6cba9
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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David Harris
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7fcc852687
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Q depends on D
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2022-08-23 08:29:59 -07:00 |
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David Harris
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e714b75888
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LSU minor edits
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2022-08-23 07:35:47 -07:00 |
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David Harris
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16a92eaf10
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Updated testbench assertions.
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2022-08-23 07:23:24 -07:00 |
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Ross Thompson
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ebe4339953
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Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
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2022-08-21 15:59:54 -05:00 |
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