33 Commits

Author	SHA1	Message	Date
David Harris	f5e2cff45a	Cause simplification	2022-05-12 23:47:21 +00:00
David Harris	c4621c5b6b	Cause simplification	2022-05-12 23:37:40 +00:00
David Harris	7daf631c13	Cause simplification	2022-05-12 23:33:35 +00:00
David Harris	803bfc4fe4	Cause simplification	2022-05-12 23:29:35 +00:00
David Harris	87dadc8208	trap/csr cleanup	2022-05-12 22:26:21 +00:00
David Harris	2eb6a65fa2	More trap/csr simplification	2022-05-12 22:04:20 +00:00
David Harris	2d8ccbd4ea	More trap/csr simplification	2022-05-12 22:00:23 +00:00
David Harris	417e36bff5	More trap/csr simplification	2022-05-12 21:55:50 +00:00
David Harris	ca6b7716e2	Simplifying trap/csr interface	2022-05-12 21:50:15 +00:00
David Harris	e2dea3bb89	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
David Harris	fb725a9e0a	Clean up unused signals	2022-05-12 14:49:58 +00:00
David Harris	a8c9f504fa	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	91472eb948	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
David Harris	8066ba45e8	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
David Harris	66424a8246	SFENCE.VMA should be illegal in user mode	2022-05-05 15:15:02 +00:00
David Harris	c100c9893b	wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts	2022-05-05 14:37:21 +00:00
David Harris	554c2b3550	Illegal instruction fault when running FPU instruction with STATUS_FS = 0	2022-05-03 18:32:01 +00:00
David Harris	9c4de0e9c1	FPU generates illegal instruction if MSTATUS.FS = 00	2022-05-03 11:56:31 +00:00
David Harris	0ede295e88	Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields	2022-04-25 14:49:00 +00:00
David Harris	855d68afde	WFI should set EPC to PC+4	2022-04-14 17:05:22 +00:00
David Harris	6966554ee8	Fixed bug with CSRRS/CSRRC for MIP/SIP	2022-04-03 20:18:25 +00:00
Ross Thompson	5ef6cde52e	Added more ILA signals.	2022-04-02 16:39:45 -05:00
bbracker	54b9745a75	big interrupts refactor	2022-03-30 13:22:41 -07:00
bbracker	9f60256f22	1st attempt at multiple channel PLIC	2022-03-24 17:08:10 -07:00
David Harris	aa990be959	removed csrn and all of its outputs because depricated	2022-02-15 19:59:29 +00:00
David Harris	ed8ac3d881	Just needed to recompile - all good. Now removed uretM because N-mode is depricated	2022-02-15 19:48:49 +00:00
David Harris	5ef8f6bc7e	Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.	2022-02-15 19:20:41 +00:00
Ross Thompson	ec44774c77	Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv	2022-01-20 16:39:54 -06:00
Ross Thompson	5cf686429d	Merged in the debug ila updates.	2022-01-18 17:29:21 -06:00
Ross Thompson	fdc17f5017	Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.	2022-01-18 17:19:33 -06:00
Ross Thompson	55456e465c	Added icache access and icache miss to performance counters.	2022-01-09 22:56:56 -06:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00