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9,631 Commits 4 Branches 2 Tags 53 MiB
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Author SHA1 Message Date
David Harris
7360be1234 Legalized PMPconfig WARL 2024-07-25 09:43:54 -07:00
David Harris
faa1378920 Legalized PMPconfig WARL 2024-07-25 09:43:54 -07:00
David Harris
c637e40058 CHeck legal rnum field when decoding aes64ks1i 2024-07-25 09:19:23 -07:00
David Harris
d5af25ffbf CHeck legal rnum field when decoding aes64ks1i 2024-07-25 09:19:23 -07:00
Jacob Pease
6fc10adc25 Added ability to split boot.memfile into boot.mem and data.mem. 2024-07-25 11:19:15 -05:00
Jacob Pease
336a413f31 Added ability to split boot.memfile into boot.mem and data.mem. 2024-07-25 11:19:15 -05:00
David Harris
7234abebef Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt 2024-07-25 09:09:13 -07:00
David Harris
5bf7250687 Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt 2024-07-25 09:09:13 -07:00
David Harris
337e40ac1b Issue #894: trap on floating-point ops with reserved rounding modes 2024-07-25 06:59:58 -07:00
David Harris
f7dd49cc6c Issue #894: trap on floating-point ops with reserved rounding modes 2024-07-25 06:59:58 -07:00
Jacob Pease
02bb9b0b8b Fixed SDCCLK name discrepency. 2024-07-24 22:48:31 -05:00
Jacob Pease
0dae881a0d Fixed SDCCLK name discrepency. 2024-07-24 22:48:31 -05:00
Jacob Pease
a34836c08b Commented out references to old axi IP from wally.tcl. 2024-07-24 22:47:15 -05:00
Jacob Pease
ebdf25a53b Commented out references to old axi IP from wally.tcl. 2024-07-24 22:47:15 -05:00
Jacob Pease
ffec8cfb20 Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram. 2024-07-24 22:46:24 -05:00
Jacob Pease
2caf9e93be Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram. 2024-07-24 22:46:24 -05:00
Jacob Pease
36d330a173 Masked lower byte when writing to DLL. 2024-07-24 22:44:27 -05:00
Jacob Pease
d15be492cb Masked lower byte when writing to DLL. 2024-07-24 22:44:27 -05:00
Jacob Pease
a97c7f0b58 Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future 2024-07-24 22:43:47 -05:00
Jacob Pease
286d80de7e Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future 2024-07-24 22:43:47 -05:00
Jacob Pease
e175a41863 Added uart header to gpt.c. 2024-07-24 22:43:16 -05:00
Jacob Pease
0107a400d1 Added uart header to gpt.c. 2024-07-24 22:43:16 -05:00
Jordan Carlin
308deba1fb Linux readme updates 2024-07-24 20:19:30 -07:00
Jordan Carlin
4b86f85904
Linux readme updates 2024-07-24 20:19:30 -07:00
Jordan Carlin
204fd2e9ff Update buildroot makefile to test for write access to $RISCV and remove separate sudo/no_sudo versions (just run the makefile as sudo if needed) 2024-07-24 20:19:30 -07:00
Jordan Carlin
a9cd457536
Update buildroot makefile to test for write access to $RISCV and remove separate sudo/no_sudo versions (just run the makefile as sudo if needed) 2024-07-24 20:19:30 -07:00
Jordan Carlin
6d77b22281 Automatically determine number of threads to use in wally-tool-chain-install 2024-07-24 20:19:30 -07:00
Jordan Carlin
676c6b88a0
Automatically determine number of threads to use in wally-tool-chain-install 2024-07-24 20:19:30 -07:00
Jordan Carlin
602d126776 Build nproc linux 2024-07-24 20:19:30 -07:00
Jordan Carlin
e6b3257862
Build nproc linux 2024-07-24 20:19:30 -07:00
Jordan Carlin
c8519ce54f Build testvectors with buildroot 2024-07-24 20:19:30 -07:00
Jordan Carlin
85b98af958
Build testvectors with buildroot 2024-07-24 20:19:30 -07:00
Jordan Carlin
04b8739756 Add cpio to installation for buildroot 2024-07-24 19:55:18 -07:00
Jordan Carlin
bbf90b1f4b
Add cpio to installation for buildroot 2024-07-24 19:55:18 -07:00
David Harris
5ac02c79c6 Merge pull request #892 from ross144/main 
Adds synthesizable RVVI FPGA hardware
 2024-07-24 12:21:36 -07:00
David Harris
2c7bc7038e
Merge pull request #892 from ross144/main 
Adds synthesizable RVVI FPGA hardware
 2024-07-24 12:21:36 -07:00
Rose Thompson
5a6e32576d Fixed the reset bug in wallyTracer. 2024-07-24 13:32:46 -05:00
Rose Thompson
ce61429bdf Fixed the reset bug in wallyTracer. 2024-07-24 13:32:46 -05:00
Rose Thompson
994386f12c Removed unused file. 2024-07-24 13:30:25 -05:00
Rose Thompson
5cae55561e Removed unused file. 2024-07-24 13:30:25 -05:00
Rose Thompson
9053923d92 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-07-24 13:14:25 -05:00
Rose Thompson
df88939bcb Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-07-24 13:14:25 -05:00
Rose Thompson
13db14db6b Factored out the rvvi testbench code into rvvitbwrapper. 2024-07-24 13:10:57 -05:00
Rose Thompson
d0a5b278b7 Factored out the rvvi testbench code into rvvitbwrapper. 2024-07-24 13:10:57 -05:00
Rose Thompson
c11036358a Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. 2024-07-24 12:47:50 -05:00
Rose Thompson
b1a711ae0f Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. 2024-07-24 12:47:50 -05:00
Rose Thompson
fb1869fcb9 Updated verilog-ethernet to remove all verilator warnings or at least suppress them. 2024-07-24 10:13:03 -05:00
Rose Thompson
27f89fcdbd Updated verilog-ethernet to remove all verilator warnings or at least suppress them. 2024-07-24 10:13:03 -05:00
Jordan Carlin
07ac498623 Switch to logger function and fix exit codes 2024-07-23 23:42:03 -07:00
Jordan Carlin
bb5c9f9ead
Switch to logger function and fix exit codes 2024-07-23 23:42:03 -07:00