Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Jordan Carlin
ef778da98d
Eliminate more logical operators and replace with bitwise
2024-05-15 10:50:23 -07:00
David Harris
ac9a21873d
Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test
2024-04-06 10:34:21 -07:00
Rose Thompson
081cf5be55
Fixed the CacheHit logger bug.
2024-03-28 13:40:01 -05:00
David Harris
aff61ea97a
Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator
2023-12-13 11:33:59 -08:00
David Harris
1f57df7f8b
Fixed reference to deleted atomic signal in cache
2023-11-23 20:29:10 -08:00
Rose Thompson
bc935b1b3b
Fixed second bug in the logger script when branch logging enabled but counter logger not.
2023-11-15 14:56:02 -06:00
Rose Thompson
5d4a89b27c
Fixed bug in the btb branch logging.
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We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
2023-11-15 14:51:47 -06:00
David Harris
bddd2d573e
Shortened path to PCSrcE in logger to avoid problematic hierarchical reference
2023-11-05 07:06:53 -08:00
Ross Thompson
59022099c7
Fixed the icache and dcache overlogging issue.
2023-07-14 15:47:05 -05:00
Ross Thompson
27f6f00402
Changes for xcelium.
2023-07-07 18:22:28 -05:00
Ross Thompson
85567841eb
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
301d54fea8
Significant refactoring of testbench.
2023-06-14 17:02:49 -05:00
