Rose Thompson
24609f0b7f
Now have configurations to switch between supporting RVVI over ethernet.
2024-07-22 10:51:13 -05:00
Rose Thompson
00840e4893
Made the fpga top level configurable between rvvi synth and not.
2024-07-19 17:35:30 -05:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
...
Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933
Cleanup in prep to merge the rvvi branch into main.
2024-07-19 15:48:20 -05:00
Rose Thompson
ce2cc48642
Updated verilog-ethernet to be compatible with wally.
2024-07-19 13:36:26 -05:00
Rose Thompson
a324e79b6f
Updated the ethernet frame gap for a faster computer.
2024-07-19 13:12:13 -05:00
Rose Thompson
9c1779a2d5
Added some documenation about sparse-checkout for verilog-ethernet submodule.
2024-07-19 13:11:48 -05:00
Rose Thompson
79d0cb96c2
Added verilog-ethernet as a submodule. Hoping we can make use of sparse-checkout as there are so many files in this repo.
2024-07-18 18:22:26 -05:00
Ross Thompson
c72f0fd504
Added csr comparison.
2024-07-11 10:49:06 -05:00
Ross Thompson
abf9da01ab
code cleanup.
2024-07-11 10:41:34 -05:00
Ross Thompson
f0096f5a43
Yay. It's actually working! The FPGA/ImperasDV hybrid is working.
2024-07-10 15:10:37 -05:00
Ross Thompson
e6dc962d11
Yay! the trigger is correctly working now!
2024-07-10 12:05:10 -05:00
Ross Thompson
cf986b5fb8
Really close to having the trigger in module work.
...
Can trigger on the data of the correct frame, but trigger in is still not
working.
2024-07-09 19:04:51 -05:00
Ross Thompson
6734685333
Fixed connection bugs in the top level fpga which preventing sending ethernet frames back to the trigger in unit.
2024-07-09 19:04:18 -05:00
Ross Thompson
e0a1f0e39f
Really close now.
2024-07-09 14:21:43 -05:00
Ross Thompson
e488ee7225
Correctly sending the ethernet frame on a mismatch. Now just need to get vivado to actually trigger.
2024-07-09 14:16:13 -05:00
Ross Thompson
fd170a6583
Getting closer.
2024-07-09 14:09:56 -05:00
Ross Thompson
bf69a2e1cd
Updated to use the newest imperasDV.
2024-07-09 12:30:18 -05:00
Ross Thompson
dc97ee5f82
Have some sample code which I know works transmisting a packet.
2024-07-02 09:12:34 -07:00
Ross Thompson
ccf4bb8ddc
Maybe have the incircuit trigger working.
2024-06-26 16:15:46 -07:00
Ross Thompson
612a281f62
Added module to receive ethernet frame and trigger the ila.
2024-06-26 11:05:31 -07:00
Ross Thompson
74189e1e4b
Have vivado triggering the ILA after the mismatch but the latency is way too long.
2024-06-25 17:04:14 -07:00
Ross Thompson
fa26c9a8b5
Added pipe to vivado to create ila trigger from rvvidaemon.
2024-06-25 13:07:46 -07:00
Ross Thompson
249d58244a
It's working!!!!!!
2024-06-20 15:48:30 -07:00
Ross Thompson
1c6ebb86a3
Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
...
Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
Ross Thompson
2581ea0b74
Found the actual bug. Once the ethernet transmit fifo was full the rvvi packetizer was not correctly marking the end of the frame. First Last was held for too many cycles. Second it was assert on cycles when Valid was not high. Simulation reproduced the FPGA corrupted frames and then with the fix showed working frames.
2024-06-18 16:48:49 -07:00
Ross Thompson
00e0549c36
I know what is wrong now. The ethernet device IP is not correctly generating the mii nibble stream. Some nibbles are dropped in each 4-byte word.
...
The default input interface to the interface is 8-bit and I used 32-bit. I suspect there is a bug in the implementation for non-8-bit interfaces.
2024-06-18 07:44:19 -07:00
Ross Thompson
93829ce509
Success! We have some instructions comparing across the FPGA and IDV!
...
However I'm still losing ethernet frames.
2024-06-17 13:41:40 -07:00
Ross Thompson
598770da51
Getting much closer to a working version.
2024-06-17 12:37:10 -07:00
Ross Thompson
cccb40e4b5
Got the tracer not overrunning ethernet buffers so frames are not being dropped.
2024-06-17 09:16:24 -07:00
Ross Thompson
82b54c0887
Got IDV properly initalized.
2024-06-17 09:15:59 -07:00
Ross Thompson
47523c97ac
Getting closer to figuring out the lost ethernet frame bugs.
2024-06-13 15:46:54 -07:00
Ross Thompson
c9f51df34a
Fixed bug in rvvi reset.
2024-06-12 14:47:32 -07:00
Ross Thompson
323dbd348e
Progress.
2024-06-12 12:54:21 -07:00
Ross Thompson
f5d4db68b1
Modified rvvidaemon to populate a struct with all the relavent fields.
2024-06-12 08:56:16 -07:00
Ross Thompson
3e7d07dfb6
Better.
2024-06-11 17:14:59 -07:00
Ross Thompson
8bce2fc739
Getting closer.
2024-06-11 16:21:53 -07:00
Ross Thompson
c9f3da51cb
getting closer to full reconstruction of rvvi.
2024-06-11 15:35:35 -07:00
Ross Thompson
3d9f796f21
Better parsing of rvvi.
2024-06-11 14:36:34 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
Ross Thompson
49912589f5
Added rvviApi.h to rvvidaemon.
2024-06-10 17:57:24 -07:00
Ross Thompson
e16cf9d739
Added Makefile to compile rvvidaemon
2024-06-10 16:56:53 -07:00
Rose Thompson
72c1374d9c
Minor code cleanup.
2024-06-04 15:11:57 -05:00
Rose Thompson
f0ed780745
progress.
2024-06-04 15:11:03 -05:00
Rose Thompson
07d66c246c
Update.
2024-06-04 11:59:17 -05:00
Rose Thompson
08ff88f428
On the way towards complete reconstruction of the RVVI trace.
2024-06-04 11:47:46 -05:00
Rose Thompson
fc62f80407
Closer to fully working hardware tracer.
2024-06-04 11:31:05 -05:00
Rose Thompson
80f98b3223
now have a working ethernet daemon to collect frames and partially decode into RVVI.
2024-06-04 10:20:51 -05:00
Rose Thompson
dc904cdbbb
The ethernet frame is mostly formatted correctly. Just need to reverse the byte order in the Ethernet length/type field.
2024-06-03 18:10:25 -05:00
Rose Thompson
0ca10e7ee2
Last of the branch predictor signal name updates.
2024-06-02 17:01:51 -05:00
