David Harris
de7b9c127e
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
b967bcede2
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
f7f3882cb8
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
d9e8d16bbe
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
Ross Thompson
ce937a35a8
Added tim only test to regression-wally. Minor cleanup to ifu.
2022-01-14 11:13:06 -06:00
Ross Thompson
5726b5b640
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
861450c4d6
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
87485f9f64
Improve wavefile by adding performance counters.
2022-01-12 10:53:29 -06:00
David Harris
4cae11ad28
Merged coremark changes
2022-01-10 05:09:28 +00:00
David Harris
467aac8463
Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
2022-01-10 05:04:13 +00:00
Ross Thompson
55456e465c
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
e01c8bc5f6
Added performance counters to wavefile.
2022-01-09 22:42:14 -06:00
Ross Thompson
3109fa1383
Fixed wavefile.
...
Converted coremark to use elf2hex.
2022-01-09 22:03:10 -06:00
David Harris
89ee6c778e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-09 14:39:33 +00:00
Ross Thompson
b6ae6fea27
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
573ff47763
renamed regression-wally.py to regression-wally
2022-01-07 17:47:38 +00:00
David Harris
6fafabbfad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 23:04:33 +00:00
David Harris
53637049b7
Makefile make allclean
2022-01-06 23:04:30 +00:00
Katherine Parry
631d05dcdc
some FPU test fixes
2022-01-06 23:03:20 +00:00
David Harris
8305eb80ff
Restored many of the arch32f and arch64d that had been failing because of memfile issues
2022-01-05 22:23:46 +00:00
David Harris
90dd961ea5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-05 22:10:33 +00:00
David Harris
07932ad0aa
Replaced exe2memfile with SiFive elf2hex
2022-01-05 22:10:26 +00:00
Ross Thompson
0310df96a4
Changes to wave file.
2022-01-05 14:16:59 -06:00
David Harris
d66f7c841b
Removed generate statements
2022-01-05 14:35:25 +00:00
Ross Thompson
888a60d8d6
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
David Harris
9ddc6db0a6
Removed imperas mmu tests; using wallypriv instead
2022-01-04 23:14:53 +00:00
David Harris
d1a7416028
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
