David Harris
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1196e5c191
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Moved generate statements for optional units into wallypipelinedhart
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2021-12-19 16:53:41 -08:00 |
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slmnemo
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a98dcd11ee
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Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.
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2021-11-17 14:08:08 -08:00 |
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slmnemo
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f4380faa4e
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removed .* from muldiv.sv (REAL)
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2021-11-17 13:37:50 -08:00 |
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slmnemo
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9fb26d5a61
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-17 13:23:20 -08:00 |
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slmnemo
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573f8b0c42
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Removed .*s from muldiv.sv
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2021-11-17 13:23:12 -08:00 |
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Kip Macsai-Goren
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3f76549a7d
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renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
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2021-11-17 10:53:17 -08:00 |
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David Harris
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4b57af9cff
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PIPELINE test running
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2021-11-01 12:44:35 -07:00 |
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David Harris
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708b914a65
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Lint cleanup from wallypipeliendhart
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2021-10-23 10:29:52 -07:00 |
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David Harris
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2abec36221
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Lint cleanup
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2021-10-23 09:58:52 -07:00 |
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David Harris
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7732d38c36
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lint cleaning and moved files into subdirectories
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2021-10-23 08:53:32 -07:00 |
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David Harris
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ff409d4fe7
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Lint cleanup
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2021-10-23 08:39:21 -07:00 |
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James E. Stine
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ed179b0bd9
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Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this
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2021-10-19 12:09:43 -05:00 |
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James E. Stine
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b65a4bd040
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Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2).
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2021-10-19 11:58:06 -05:00 |
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David Harris
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df0b65e483
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replaced flopenl with flopenr when clearing to 0
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2021-10-18 16:53:18 -07:00 |
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David Harris
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47f7a5db9c
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Fixed multiplier and pointed arch tests to new path in addins
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2021-10-18 15:43:59 -07:00 |
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James E. Stine
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d895fd7ee5
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Sanitization some more on mult_cs.sv
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2021-10-18 05:24:16 -05:00 |
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James E. Stine
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aafa988ca2
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Update some on mult_cs and delete DW02_mult.v
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2021-10-18 05:06:49 -05:00 |
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James E. Stine
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5a1835622c
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Add hacky hand-made carry/save multiplier - will improve
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2021-10-16 10:37:29 -05:00 |
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Skylar Litz
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d639222519
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add StallM signal back to DivStartE control
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2021-10-13 15:34:40 -07:00 |
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Shreya Sanghai
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51185478df
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made redunantmul generate DW02_multp for synopsys sythnesis
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2021-10-11 11:54:39 -07:00 |
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Shreya Sanghai
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295a3c7af2
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actually added redundant mul
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2021-10-11 11:29:13 -07:00 |
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Shreya Sanghai
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324230e2f9
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added redundant multiplier
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2021-10-11 11:20:12 -07:00 |
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David Harris
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fc39f77cba
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Starting to optimize multiplier
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2021-10-11 11:06:07 -07:00 |
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David Harris
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8a64675b02
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intdiv cleanup
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2021-10-11 08:14:21 -07:00 |
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David Harris
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a8ce4568aa
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Divider FSM simplification
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2021-10-10 22:24:14 -07:00 |
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David Harris
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a077735ecc
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Major reorganization of regression and simulation and testbenches
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2021-10-10 15:07:51 -07:00 |
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David Harris
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93e6ec96a7
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Divider cleanup
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2021-10-10 12:24:44 -07:00 |
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David Harris
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6d2d93deeb
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Simplifying divider FSM
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2021-10-10 12:21:43 -07:00 |
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David Harris
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2d09994a91
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Simplifying divider FSM
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2021-10-10 12:21:36 -07:00 |
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David Harris
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644af40855
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Moved & ~StallM from FSM into DivStartE
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2021-10-10 11:49:32 -07:00 |
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David Harris
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e93014d6d8
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Moved divide iteration register names to M stage
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2021-10-10 11:30:53 -07:00 |
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David Harris
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e8d013b106
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Simplified remainder for divide by 0
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2021-10-10 11:20:07 -07:00 |
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David Harris
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94fd682cdc
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divider control signal simplificaiton
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2021-10-10 10:55:02 -07:00 |
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David Harris
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bfe8bf3855
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Removed negedge flops from divider
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2021-10-10 10:41:13 -07:00 |
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David Harris
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99fd79c20b
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Simplified divider sign handling
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2021-10-10 08:35:26 -07:00 |
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David Harris
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eaa8be14b9
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renamed DivStart
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2021-10-10 08:32:04 -07:00 |
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David Harris
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5cb30164d4
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renamed DivSigned
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2021-10-10 08:30:19 -07:00 |
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bbracker
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25e0745a6a
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fix div restarting bug
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2021-10-07 18:55:00 -04:00 |
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David Harris
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cc41d40d61
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Divider cleaup
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2021-10-03 11:22:34 -04:00 |
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David Harris
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3398328bf1
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Divider cleanup
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2021-10-03 11:16:48 -04:00 |
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David Harris
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9809e57d0c
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Replacing XE and DE with SrcAE and SrcBE in divider
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2021-10-03 11:11:53 -04:00 |
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David Harris
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bf0061be66
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Reduced cycle count for DIVW/DIVUW by two
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2021-10-03 09:42:22 -04:00 |
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David Harris
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bd61ec544b
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Divider comments cleanup
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2021-10-03 01:12:40 -04:00 |
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David Harris
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30ec68d567
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Parameterized number of bits per cycle for integer division
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2021-10-03 01:10:15 -04:00 |
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David Harris
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078ddfd341
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Divider cleanup
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2021-10-03 00:41:41 -04:00 |
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David Harris
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8f36297569
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Added suffixes to more divider signals
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2021-10-03 00:32:58 -04:00 |
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David Harris
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dcbbee6623
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More divider cleanup
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2021-10-03 00:20:35 -04:00 |
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David Harris
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6aa2521959
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Eliminated extra inversion for subtraction in divider
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2021-10-03 00:10:12 -04:00 |
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David Harris
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371f9d9a4a
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Added more pipeline stage suffixes to divider
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2021-10-03 00:06:57 -04:00 |
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David Harris
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24bb3f4baf
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Added more pipeline stage suffixes to divider
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2021-10-02 22:54:01 -04:00 |
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