Ross Thompson
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dad6770fc3
|
Updated fpga testbench.
|
2022-08-21 14:07:26 -05:00 |
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Katherine Parry
|
0f077012c3
|
sqrt tests in regression uncommented and pass
|
2022-08-07 23:38:10 +00:00 |
|
Katherine Parry
|
8eeca3319c
|
radix-2 1 copy passes testfloat
|
2022-08-06 22:54:05 +00:00 |
|
David Harris
|
8b8f045491
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
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2022-08-03 09:33:56 -07:00 |
|
David Harris
|
6ee8036ae7
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
e3b970d3ff
|
Partitioned fma into separate files
|
2022-08-01 18:07:38 +00:00 |
|
David Harris
|
da275e3c26
|
Increased timeout threshold to avoid timeout building riscof tests on slow machine
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2022-07-27 04:05:21 +00:00 |
|
David Harris
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ae4ea00ff0
|
fixed testbench merge comflict
|
2022-07-26 06:21:46 -07:00 |
|
David Harris
|
449c80b5f7
|
More work toward riscof tests
|
2022-07-26 06:19:13 -07:00 |
|
David Harris
|
094aacdf6f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-25 23:29:08 +00:00 |
|
David Harris
|
ccf8ccfa24
|
Added rv32f tests to RV64gc
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2022-07-25 23:29:05 +00:00 |
|
David Harris
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539174f6f6
|
Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
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2022-07-25 16:23:10 -07:00 |
|
Ross Thompson
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70032bf8f4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-23 08:41:59 -05:00 |
|
Katherine Parry
|
ee7932c804
|
divider sizes reworked to match book
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2022-07-22 22:02:04 +00:00 |
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Daniel Torres
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d95b266d49
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changes to test.vh for compatability
|
2022-07-22 15:00:48 -07:00 |
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Daniel Torres
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2bbfd67082
|
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
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2022-07-22 14:58:55 -07:00 |
|
slmnemo
|
44c30ec082
|
fixed error in tests.vh
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2022-07-22 14:55:55 -07:00 |
|
slmnemo
|
170601af0b
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Added UART test to peripheral test
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2022-07-22 14:55:34 -07:00 |
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Daniel Torres
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fbe3a1af12
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 13:52:19 -07:00 |
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Daniel Torres
|
261b9aa5a1
|
commented out embench test that should be commented out
|
2022-07-22 13:52:13 -07:00 |
|
slmnemo
|
0d98ff74b4
|
Added PLIC test to regression
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2022-07-22 12:35:37 -07:00 |
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Daniel Torres
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5d7171f6f8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 11:16:09 -07:00 |
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Daniel Torres
|
526f70e772
|
commiting current changes to riscof wally tests
|
2022-07-22 11:14:04 -07:00 |
|
slmnemo
|
49565f944c
|
Added PLIC and UART tests and new functions to the test library
|
2022-07-22 07:10:39 -07:00 |
|
Daniel Torres
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bd918d37ba
|
added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
|
2022-07-21 20:58:58 -07:00 |
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Daniel Torres
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a17361870f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 12:50:04 -07:00 |
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Daniel Torres
|
6e9b4f4075
|
removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
|
2022-07-21 12:47:51 -07:00 |
|
Katherine Parry
|
270216dd02
|
radix-4 division integrated into srt - not tested
|
2022-07-21 19:38:06 +00:00 |
|
Katherine Parry
|
67c99d3d1a
|
added input enables and improved forwarding
|
2022-07-21 01:20:06 +00:00 |
|
Daniel Torres
|
d33d0d22bd
|
commented out embench 2.0 tests
|
2022-07-19 13:36:18 -07:00 |
|
Katherine Parry
|
4c2afbbc4f
|
moved Se into execute stage
|
2022-07-19 01:10:10 +00:00 |
|
Katherine Parry
|
e599f82b29
|
moved Ss to execute stage
|
2022-07-18 20:48:56 +00:00 |
|
Katherine Parry
|
921debf930
|
removed underflow from inexactct calculation
|
2022-07-18 17:51:18 +00:00 |
|
Katherine Parry
|
5bb1478859
|
renamed signals in ocde to match book
|
2022-07-18 17:31:17 +00:00 |
|
Ross Thompson
|
a88543275f
|
Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
|
2022-07-17 21:05:31 -05:00 |
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Ross Thompson
|
3670c47141
|
Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
|
2022-07-17 16:20:04 -05:00 |
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Katherine Parry
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e251022269
|
merged floating-point radix-2 divider with radix-4
|
2022-07-15 20:16:59 +00:00 |
|
Katherine Parry
|
b069cfbec2
|
fixed error in divsqrt
|
2022-07-14 18:16:00 +00:00 |
|
Katherine Parry
|
77ea4e47cb
|
removed minus 1 case in rounding
|
2022-07-13 15:01:38 -07:00 |
|
Katherine Parry
|
e05b2a07d2
|
removed warnings and took a mux out of the critical path
|
2022-07-12 18:32:17 -07:00 |
|
Katherine Parry
|
2ada8a8bc1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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Katherine Parry
|
7815b81716
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-11 18:30:29 -07:00 |
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Katherine Parry
|
b728e5054d
|
variable interations implemented in radix-4 divider
|
2022-07-11 18:30:21 -07:00 |
|
DTowersM
|
191c7a2ee3
|
added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
|
2022-07-11 21:13:09 +00:00 |
|
Katherine Parry
|
ca4fe08fd9
|
renamed FLoad2 to FStore2
|
2022-07-09 00:26:45 +00:00 |
|
Katherine Parry
|
cd53ae67d9
|
moved fpu ieu write data mux to lsu
|
2022-07-08 23:56:57 +00:00 |
|
Katherine Parry
|
3476579e02
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-08 12:30:50 -07:00 |
|
Katherine Parry
|
9ef45f36fd
|
renamed signals in cvt and prostproc
|
2022-07-08 12:30:43 -07:00 |
|
David Harris
|
d10ad0e883
|
Removed testbench code that ignores mismatch on zero signatures
|
2022-07-08 09:17:31 +00:00 |
|
DTowersM
|
5a68ff9afb
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
|
2022-07-07 23:11:35 +00:00 |
|
DTowersM
|
d55833e4f3
|
new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory
|
2022-07-07 23:11:02 +00:00 |
|
Katherine Parry
|
41c16be012
|
srt divider merged into fpu
|
2022-07-07 16:01:33 -07:00 |
|
David Harris
|
2f342c430e
|
fixing port errors
|
2022-07-07 21:57:10 +00:00 |
|
Katherine Parry
|
0b40f38f02
|
added load and store test
|
2022-07-07 21:48:51 +00:00 |
|
DTowersM
|
47a990d9f1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
|
2022-07-06 23:44:27 +00:00 |
|
DTowersM
|
1e8ccf3449
|
added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu
|
2022-07-06 23:43:57 +00:00 |
|
David Harris
|
dab87811e9
|
Removed sig4 spurious message from testbench
|
2022-07-05 03:27:14 +00:00 |
|
Katherine Parry
|
010a05f583
|
added missing files
|
2022-07-03 21:40:47 -07:00 |
|
Katherine Parry
|
1b4584e825
|
Renaming signals to match chapter
|
2022-07-03 12:26:22 -07:00 |
|
Daniel Torres
|
a384a6465b
|
reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished
|
2022-06-29 12:32:30 -07:00 |
|
Daniel Torres
|
50b9b4557c
|
added changes to testbench, tests and riscof for additional riscof compatability
|
2022-06-29 12:23:40 -07:00 |
|
slmnemo
|
448c9fdbb9
|
Add CLINT tests from book
|
2022-06-27 20:09:58 -07:00 |
|
Katherine Parry
|
f25bb4a384
|
radix-4 early termination working for special cases - not working completely
|
2022-06-27 20:43:55 +00:00 |
|
Katherine Parry
|
06f7f9b147
|
fixed commented out error and removed killprod from result selection
|
2022-06-25 01:42:23 +00:00 |
|
Katherine Parry
|
d058ec6329
|
added denormal input handeling - radix 4
|
2022-06-24 19:41:40 +00:00 |
|
Katherine Parry
|
b54d84195f
|
added radix-4 0/d handling
|
2022-06-23 22:36:19 +00:00 |
|
Katherine Parry
|
5133b08161
|
generate qsel4 in verilog
|
2022-06-23 21:38:04 +00:00 |
|
Katherine Parry
|
49067792dc
|
fixt lint error
|
2022-06-23 16:11:50 +00:00 |
|
Katherine Parry
|
4a6dee5926
|
Testfloat running division - not passing
|
2022-06-23 00:07:34 +00:00 |
|
David Harris
|
8537b883d1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-21 22:45:28 +00:00 |
|
slmnemo
|
2b2760f5bd
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-21 02:16:26 -07:00 |
|
slmnemo
|
2b2ddbcc5e
|
Added rudimentary GPIO test according to testplans in chapter 15
|
2022-06-21 02:16:21 -07:00 |
|
Katherine Parry
|
254ebf478e
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
|
Daniel Torres
|
d077199608
|
embench and testbench now support running both O2 and Os build variations without overwriting one another
|
2022-06-17 21:15:42 -07:00 |
|
Daniel Torres
|
1ef5ed8005
|
arch tests now run on spike and sail and compare signatures during build
|
2022-06-17 20:53:15 -07:00 |
|
Daniel Torres
|
dcdd3702c3
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
|
3a5c02b44a
|
arch bug fixes and testbench changes
|
2022-06-17 15:07:16 -07:00 |
|
David Harris
|
ecd733942a
|
Removed testbench.sv.bak
|
2022-06-14 22:04:38 +00:00 |
|
DTowersM
|
919c1818a8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-13 23:34:35 +00:00 |
|
DTowersM
|
1f4d56ba32
|
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
|
2022-06-13 23:23:57 +00:00 |
|
Katherine Parry
|
31fd8772cf
|
postprocessing unit created and passing all tests
|
2022-06-13 22:47:51 +00:00 |
|
DTowersM
|
4bbe5eeecd
|
simplified coremark
|
2022-06-10 19:15:17 +00:00 |
|
slmnemo
|
284e0395a0
|
Merge branch 'main' into cacheburstmode
|
2022-06-08 02:21:33 +00:00 |
|
DTowersM
|
a190342b8a
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-07 23:58:58 +00:00 |
|
DTowersM
|
02a424d65b
|
modified testbench.sv- now works with coremark
|
2022-06-07 23:58:50 +00:00 |
|
DTowersM
|
e324db71b4
|
cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000
|
2022-06-07 23:27:54 +00:00 |
|
DTowersM
|
df330961b8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-07 06:03:19 +00:00 |
|
DTowersM
|
590cf243bb
|
added support for 64 bit rv tests
|
2022-06-07 06:02:23 +00:00 |
|
Katherine Parry
|
cfcaddf8aa
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-06 16:06:54 +00:00 |
|
Katherine Parry
|
8fa0fc4229
|
fma synth warnings and errors removed
|
2022-06-06 16:06:04 +00:00 |
|
slmnemo
|
3fe78c9084
|
Fixed recurrent issue with testbench where it would never stop
|
2022-06-03 18:56:24 -07:00 |
|
DTowersM
|
caaf56cbf7
|
testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh
|
2022-06-03 22:07:14 +00:00 |
|
Katherine Parry
|
6b39b8c702
|
fixed compilation errors
|
2022-06-03 15:34:17 +00:00 |
|
Katherine Parry
|
8420b1e87c
|
removed some debuging code accedentally pushed
|
2022-06-02 22:45:19 +00:00 |
|
slmnemo
|
c8515001a2
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-02 12:54:08 -07:00 |
|
Katherine Parry
|
9a09ee3a35
|
fpu paramaterized - except fdivsqrt
|
2022-06-02 19:50:28 +00:00 |
|
slmnemo
|
88454aa2ab
|
Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do"
This reverts commit 89c7438424.
|
2022-06-02 12:45:21 -07:00 |
|
slmnemo
|
ad9e85beb9
|
Revert "Fixed buildroot by adding a second ."
This reverts commit 8b27c1884e.
|
2022-06-02 12:43:59 -07:00 |
|
David Harris
|
197b588193
|
Cleaned up test cases in testbench
|
2022-06-02 08:44:28 -07:00 |
|
slmnemo
|
c16c5beef5
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-02 02:52:03 +00:00 |
|