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4,260 Commits 5 Branches 2 Tags 53 MiB
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Author SHA1 Message Date
cturek
31db938e7e Added adder input selection to on the fly converter 2022-07-13 17:47:27 +00:00
cturek
bb7e73abf0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-13 17:36:56 +00:00
Katherine Parry
26e39dd325 removed the +1 in the cvt 2022-07-13 09:41:35 -07:00
Katherine Parry
e05b2a07d2 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
cturek
5c9f011561 little fix 2022-07-12 23:04:33 +00:00
cturek
ed9106128f Square root implemented 2022-07-12 22:45:54 +00:00
Katherine Parry
452b017f9a found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
cturek
9d4acc9ddb C register and other various fixes 2022-07-12 22:18:56 +00:00
cturek
3483b92480 On the fly conversion for square root 2022-07-12 02:21:38 +00:00
Katherine Parry
5c0ecfa433 forgot a file 2022-07-11 18:31:51 -07:00
Katherine Parry
7815b81716 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-11 18:30:29 -07:00
Katherine Parry
b728e5054d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
DTowersM
191c7a2ee3 added some preliminary support for coremark XLEN=32, made sure rv64 not impacted 2022-07-11 21:13:09 +00:00
DTowersM
a310ef4ded switched coremark to 10 iterations 2022-07-11 17:20:38 +00:00
David Harris
2bc8ff555b added comment about checking SRAM size 2022-07-10 12:48:51 +00:00
David Harris
9cb675b2e4 added comment about RAMs in cacheway 2022-07-10 12:47:34 +00:00
David Harris
ad92d0876e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-10 03:18:30 +00:00
Madeleine Masser-Frye
0dc3c9462b improved command line synth functionality 2022-07-09 04:51:23 +00:00
Madeleine Masser-Frye
b196b6b504 explanations and modifications for general ppa use 2022-07-09 03:24:47 +00:00
Madeleine Masser-Frye
19db618b7f syntheses now write alib in their own directories 2022-07-09 02:40:41 +00:00
Katherine Parry
ca4fe08fd9 renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
Madeleine Masser-Frye
853a3a5df1 remove outdated scripts 2022-07-08 22:52:53 +00:00
Madeleine Masser-Frye
8dbb45519e tweaks to run synth without error 2022-07-08 22:52:10 +00:00
Madeleine Masser-Frye
a84aa36530 cleaned up old commands and commented 2022-07-08 22:39:53 +00:00
Madeleine Masser-Frye
79b93e776e condensed cleanup, changed bpred_size to 4, moved synth hdl into own directory 2022-07-08 22:29:18 +00:00
Madeleine Masser-Frye
8432c6331c told dc to look in synth directory for hdl and WORK 2022-07-08 22:16:34 +00:00
David Harris
64dd4f1644 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-08 22:00:53 +00:00
David Harris
8c9f483133 CoreMark makefile and printing improvements 2022-07-08 22:00:50 +00:00
cturek
2dc074ea93 F Selection 2022-07-08 21:53:52 +00:00
DTowersM
3e19500fc8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-08 21:25:58 +00:00
DTowersM
f36b31a78b added PORT_CFLAGS and some WIP 32bit support 2022-07-08 21:25:52 +00:00
Madeleine Masser-Frye
27ec022df9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-08 20:42:04 +00:00
Madeleine Masser-Frye
56f002b707 made parallel synthesis in python command line based 2022-07-08 20:41:59 +00:00
Katherine Parry
3476579e02 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-08 12:30:50 -07:00
Katherine Parry
9ef45f36fd renamed signals in cvt and prostproc 2022-07-08 12:30:43 -07:00
James Stine
c5dfefe669 Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00
slmnemo
43549b10fb Fixed error in gpio test 2022-07-08 02:27:16 -07:00
David Harris
d10ad0e883 Removed testbench code that ignores mismatch on zero signatures 2022-07-08 09:17:31 +00:00
David Harris
c72e4d43d2 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-08 09:09:07 +00:00
David Harris
381f3298d8 Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc 2022-07-08 09:09:02 +00:00
David Harris
1ce0975366 Adjusting byte writes to RAM 2022-07-08 08:45:21 +00:00
David Harris
3f9e662201 Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables 2022-07-08 08:44:37 +00:00
David Harris
9b6d9666c5 Removed unused swbytemask from CLINT 2022-07-08 08:43:24 +00:00
Madeleine Masser-Frye
023b31a4d2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-08 08:02:19 +00:00
Madeleine Masser-Frye
8f0f626140 made wally synth flow shell based 2022-07-08 08:02:11 +00:00
Madeleine Masser-Frye
8e6aa12b2b restore flatten 2022-07-08 08:01:10 +00:00
David Harris
76ab5e7993 makefile 2022-07-07 16:43:03 -07:00
David Harris
10ebcd1f95 CoreMark makefile tuning 2022-07-07 16:42:30 -07:00